axi: Add AXI lite dual-port RAM module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-07 16:28:40 -08:00 · 2025-02-27 00:58:30 -08:00
parent 55c097f47d
commit ad3042e090
5 changed files with 669 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -30,6 +30,7 @@ To facilitate the dual-license model, contributions to the project can only be a
    *  SV interface for AXI lite
    *  Register slice
    *  Single port RAM
+    *  Dual-port RAM
 *  AXI stream
    *  SV interface for AXI stream
    *  Register slice