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pcie: Rename enable to en in PCIe US AXI lite master

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-29 17:59:33 -07:00
parent 63c961cab4
commit b3441f6408
3 changed files with 5 additions and 5 deletions
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4
src/pcie/rtl/taxi_pcie_us_axil_master.sv
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@@ -36,7 +36,7 @@ module taxi_pcie_us_axil_master
* Configuration
*/
input wire logic [15:0] completer_id,
input wire logic completer_id_enable,
input wire logic completer_id_en,
/*
* Status
@@ -262,7 +262,7 @@ always_comb begin
cpl_tlp_hdr[63:48] = requester_id_reg;
cpl_tlp_hdr[71:64] = tag_reg;
cpl_tlp_hdr[87:72] = completer_id;
cpl_tlp_hdr[88] = completer_id_enable;
cpl_tlp_hdr[88] = completer_id_en;
cpl_tlp_hdr[91:89] = tc_reg;
cpl_tlp_hdr[94:92] = attr_reg;
cpl_tlp_hdr[95] = 1'b0; // force ECRC

2
src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.py
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@@ -124,7 +124,7 @@ class TB(object):
self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
dut.completer_id.setimmediatevalue(0)
dut.completer_id_enable.setimmediatevalue(0)
dut.completer_id_en.setimmediatevalue(0)
# monitor error outputs
self.stat_err_cor_asserted = False

4
src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.sv
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@@ -59,7 +59,7 @@ taxi_axil_if #(
) m_axil();
logic [15:0] completer_id;
logic completer_id_enable;
logic completer_id_en;
logic stat_err_cor;
logic stat_err_uncor;
@@ -85,7 +85,7 @@ uut (
* Configuration
*/
.completer_id(completer_id),
.completer_id_enable(completer_id_enable),
.completer_id_en(completer_id_en),
/*
* Status