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eth: Update XUPP3R/XUSP3S example design to use 32-bit MACs at 10G

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-05 22:02:32 -08:00
parent 66a93a734f
commit b97eb139ca
13 changed files with 159 additions and 25 deletions
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2
src/eth/example/XUPP3R/fpga/fpga_XUPP3R/Makefile
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@@ -37,7 +37,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
# Configuration
#CONFIG_TCL_FILES = config.tcl
CONFIG_TCL_FILES = config.tcl
include ../common/vivado.mk

22
src/eth/example/XUPP3R/fpga/fpga_XUPP3R/config.tcl Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "64"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]

4
src/eth/example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile
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@@ -34,10 +34,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
# Configuration
#CONFIG_TCL_FILES = config.tcl
CONFIG_TCL_FILES = config.tcl
include ../common/vivado.mk

22
src/eth/example/XUPP3R/fpga/fpga_XUPP3R_10g/config.tcl Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "32"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]

3
src/eth/example/XUPP3R/fpga/fpga_XUSP3S/Makefile
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@@ -37,7 +37,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
# Configuration
#CONFIG_TCL_FILES = config.tcl
CONFIG_TCL_FILES = config.tcl
include ../common/vivado.mk
@@ -156,4 +156,3 @@ flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
echo "exit" >> flash$*.tcl
vivado -nojournal -nolog -mode batch -source flash$*.tcl

22
src/eth/example/XUPP3R/fpga/fpga_XUSP3S/config.tcl Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "64"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]

5
src/eth/example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile
View File

@@ -34,10 +34,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
# Configuration
#CONFIG_TCL_FILES = config.tcl
CONFIG_TCL_FILES = config.tcl
include ../common/vivado.mk
@@ -156,4 +156,3 @@ flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
echo "exit" >> flash$*.tcl
vivado -nojournal -nolog -mode batch -source flash$*.tcl

22
src/eth/example/XUPP3R/fpga/fpga_XUSP3S_10g/config.tcl Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: MIT
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
set params [dict create]
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "32"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {
lappend param_list $name=$value
}
set_property generic $param_list [get_filesets sources_1]

24
src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv
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@@ -17,13 +17,21 @@ Authors:
*/
module fpga_core #
(
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
// device family
parameter string FAMILY = "virtexuplus",
// Board configuration
parameter PORT_CNT = 4,
parameter GTY_QUAD_CNT = PORT_CNT,
parameter GTY_CNT = GTY_QUAD_CNT*4,
parameter GTY_CLK_CNT = GTY_QUAD_CNT
parameter GTY_CLK_CNT = GTY_QUAD_CNT,
// 10G/25G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 64
)
(
@@ -189,12 +197,12 @@ assign eth_port_lpmode = '0;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire eth_gty_rx_status[GTY_CNT];
@@ -226,7 +234,7 @@ for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
.O (eth_gty_mgt_refclk[n]),
.ODIV2 (eth_gty_mgt_refclk_int)
);
end else begin
IBUFDS_GTE3 ibufds_gte4_eth_gty_mgt_refclk_inst (
@@ -236,7 +244,7 @@ for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
.O (eth_gty_mgt_refclk[n]),
.ODIV2 (eth_gty_mgt_refclk_int)
);
end
BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
@@ -279,12 +287,14 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.CNT(4),
// GT config
.CFG_LOW_LATENCY(1),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
// GT type
.GT_TYPE("GTY"),
// PHY parameters
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W),
.PADDING_EN(1'b1),
.DIC_EN(1'b1),
.MIN_FRAME_LEN(64),

14
src/eth/example/XUPP3R/fpga/rtl/fpga_xupp3r.sv
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@@ -17,9 +17,16 @@ Authors:
*/
module fpga #
(
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtexuplus"
// device family
parameter string FAMILY = "virtexuplus",
// 10G/25G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 64
)
(
/*
@@ -385,7 +392,10 @@ fpga_core #(
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
.GTY_CLK_CNT(GTY_CLK_CNT),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.MAC_DATA_W(MAC_DATA_W)
)
core_inst (
/*

14
src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
View File

@@ -17,9 +17,16 @@ Authors:
*/
module fpga #
(
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtexu"
// device family
parameter string FAMILY = "virtexu",
// 10G/25G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 64
)
(
/*
@@ -385,7 +392,10 @@ fpga_core #(
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
.GTY_CLK_CNT(GTY_CLK_CNT),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.MAC_DATA_W(MAC_DATA_W)
)
core_inst (
/*

3
src/eth/example/XUPP3R/fpga/tb/fpga_core/Makefile
View File

@@ -45,6 +45,9 @@ export PARAM_PORT_CNT := 4
export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
export PARAM_CFG_LOW_LATENCY := "1'b1"
export PARAM_COMBINED_MAC_PCS := "1'b1"
export PARAM_MAC_DATA_W := "64"
ifeq ($(SIM), icarus)
PLUSARGS += -fst

27
src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -13,6 +13,7 @@ import logging
import os
import sys
import pytest
import cocotb_test.simulator
import cocotb
@@ -56,12 +57,20 @@ class TB:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.CFG_LOW_LATENCY.value:
clk = 2.482
gbx_cfg = (66, [64, 65])
if ch.ch_inst.DATA_W.value == 64:
if ch.ch_inst.CFG_LOW_LATENCY.value:
clk = 2.482
gbx_cfg = (66, [64, 65])
else:
clk = 2.56
gbx_cfg = None
else:
clk = 2.56
gbx_cfg = None
if ch.ch_inst.CFG_LOW_LATENCY.value:
clk = 3.102
gbx_cfg = (66, [64, 65])
else:
clk = 3.2
gbx_cfg = None
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
@@ -112,6 +121,8 @@ async def mac_test(tb, source, sink):
for k in range(1200):
await RisingEdge(tb.dut.clk_125mhz)
sink.clear()
tb.log.info("Multiple small packets")
count = 64
@@ -192,7 +203,8 @@ def process_f_files(files):
return list(lst.values())
def test_fpga_core(request):
@pytest.mark.parametrize("mac_data_w", [32, 64])
def test_fpga_core(request, mac_data_w):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@@ -219,6 +231,9 @@ def test_fpga_core(request):
parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
parameters['CFG_LOW_LATENCY'] = "1'b1"
parameters['COMBINED_MAC_PCS'] = "1'b1"
parameters['MAC_DATA_W'] = mac_data_w
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}