eth: Fix Alveo example design UART handling

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2026-04-09 05:18:44 -07:00 · 2026-04-05 18:26:53 -07:00
parent 9e39b00d51
commit bbe4353c3a
8 changed files with 28 additions and 16 deletions
--- a/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
+++ b/src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
@@ -48,8 +48,8 @@ module fpga #
    /*
     * UART
     */
-    output wire logic [UART_CNT-1:0]  uart_txd,
-    input  wire logic [UART_CNT-1:0]  uart_rxd,
+    output wire logic                 uart_txd[UART_CNT],
+    input  wire logic                 uart_rxd[UART_CNT],

    /*
     * Ethernet: QSFP28