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eth: Fix Alveo example design UART handling

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-04-05 18:26:53 -07:00
parent 9e39b00d51
commit bbe4353c3a
8 changed files with 28 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/eth/example/Alveo/fpga/rtl/fpga_au200.sv
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@@ -252,6 +252,12 @@ assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0]; assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
wire uart_txd_int[1];
wire uart_rxd_int[1];
assign uart_txd = uart_txd_int[0];
assign uart_rxd_int[0] = uart_rxd;
fpga_core #( fpga_core #(
.SIM(SIM), .SIM(SIM),
.VENDOR(VENDOR), .VENDOR(VENDOR),
@@ -289,8 +295,8 @@ core_inst (
/* /*
* UART * UART
*/ */
.uart_txd(uart_txd), .uart_txd(uart_txd_int),
.uart_rxd(uart_rxd), .uart_rxd(uart_rxd_int),
/* /*
* Ethernet * Ethernet

10
src/eth/example/Alveo/fpga/rtl/fpga_au280.sv
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@@ -215,6 +215,12 @@ assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0]; assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
wire uart_txd_int[1];
wire uart_rxd_int[1];
assign uart_txd = uart_txd_int[0];
assign uart_rxd_int[0] = uart_rxd;
fpga_core #( fpga_core #(
.SIM(SIM), .SIM(SIM),
.VENDOR(VENDOR), .VENDOR(VENDOR),
@@ -252,8 +258,8 @@ core_inst (
/* /*
* UART * UART
*/ */
.uart_txd(uart_txd), .uart_txd(uart_txd_int),
.uart_rxd(uart_rxd), .uart_rxd(uart_rxd_int),
/* /*
* Ethernet * Ethernet

4
src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv
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@@ -44,8 +44,8 @@ module fpga #
/* /*
* UART * UART
*/ */
output wire logic [UART_CNT-1:0] uart_txd, output wire logic uart_txd[UART_CNT],
input wire logic [UART_CNT-1:0] uart_rxd, input wire logic uart_rxd[UART_CNT],
/* /*
* Ethernet: QSFP28 * Ethernet: QSFP28

4
src/eth/example/Alveo/fpga/rtl/fpga_au50.sv
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@@ -43,8 +43,8 @@ module fpga #
/* /*
* UART * UART
*/ */
output wire logic [UART_CNT-1:0] uart_txd, output wire logic uart_txd[UART_CNT],
input wire logic [UART_CNT-1:0] uart_rxd, input wire logic uart_rxd[UART_CNT],
/* /*
* Ethernet: QSFP28 * Ethernet: QSFP28

4
src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
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@@ -48,8 +48,8 @@ module fpga #
/* /*
* UART * UART
*/ */
output wire logic [UART_CNT-1:0] uart_txd, output wire logic uart_txd[UART_CNT],
input wire logic [UART_CNT-1:0] uart_rxd, input wire logic uart_rxd[UART_CNT],
/* /*
* Ethernet: QSFP28 * Ethernet: QSFP28

4
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
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@@ -59,8 +59,8 @@ module fpga_core #
/* /*
* UART * UART
*/ */
output wire [UART_CNT-1:0] uart_txd, output wire uart_txd[UART_CNT],
input wire [UART_CNT-1:0] uart_rxd, input wire uart_rxd[UART_CNT],
/* /*
* Ethernet * Ethernet

4
src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv
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@@ -42,8 +42,8 @@ module fpga #
/* /*
* UART * UART
*/ */
output wire logic [UART_CNT-1:0] uart_txd, output wire logic uart_txd[UART_CNT],
input wire logic [UART_CNT-1:0] uart_rxd, input wire logic uart_rxd[UART_CNT],
/* /*
* Ethernet: QSFP28 * Ethernet: QSFP28

4
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -43,8 +43,8 @@ class TB:
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1) self.uart_sources = [UartSource(pin, baud=3000000, bits=8, stop_bits=1) for pin in dut.uart_rxd]
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1) self.uart_sinks = [UartSink(pin, baud=3000000, bits=8, stop_bits=1) for pin in dut.uart_txd]
self.qsfp_sources = [] self.qsfp_sources = []
self.qsfp_sinks = [] self.qsfp_sinks = []