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pcie: Tie off AXIL user signals in PCIe AXI lite master module

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-02-21 02:48:18 -08:00
parent 1e6f5531d1
commit be80d4e964
1 changed files with 3 additions and 0 deletions
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src/pcie/rtl/taxi_pcie_us_axil_master.sv
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@@ -201,13 +201,16 @@ assign s_axis_cq.tready = s_axis_cq_tready_reg;
assign m_axil_wr.awaddr = m_axil_addr_reg; assign m_axil_wr.awaddr = m_axil_addr_reg;
assign m_axil_wr.awprot = 3'b010; assign m_axil_wr.awprot = 3'b010;
assign m_axil_wr.awuser = '0;
assign m_axil_wr.awvalid = m_axil_awvalid_reg; assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg; assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg; assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wuser = '0;
assign m_axil_wr.wvalid = m_axil_wvalid_reg; assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg; assign m_axil_wr.bready = m_axil_bready_reg;
assign m_axil_rd.araddr = m_axil_addr_reg; assign m_axil_rd.araddr = m_axil_addr_reg;
assign m_axil_rd.arprot = 3'b010; assign m_axil_rd.arprot = 3'b010;
assign m_axil_rd.aruser = '0;
assign m_axil_rd.arvalid = m_axil_arvalid_reg; assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg; assign m_axil_rd.rready = m_axil_rready_reg;