bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2026-09-05 03:25:15 -07:00
Code Issues Packages Projects Releases Wiki Activity

eth: Add os_match and idle_match to BASE-R model

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-07-11 10:46:37 -07:00
parent 1a54aa4a97
commit be9197a231
1 changed files with 22 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/eth/tb/baser.py
View File

@@ -594,6 +594,8 @@ class BaseRSerdesSink:
self.os = None
self.os_sig = False
self.os_match_cnt = 0
self.idle_match_cnt = 0
self.width = len(self.data)
self.byte_size = 8
@@ -673,6 +675,12 @@ class BaseRSerdesSink:
self.os = None
return ret
def get_os_match(self):
return self.os_match_cnt > 2
def get_idle_match(self):
return self.idle_match_cnt > 2
def _recv(self, frame, compact=True):
if self.queue.empty():
self.active_event.clear()
@@ -845,6 +853,8 @@ class BaseRSerdesSink:
# C7 C6 C5 C4 C3 C2 C1 C0 BT
dl = ctrl
cl = [1]*8
self.os_match_cnt = 0
self.idle_match_cnt += 1
elif db[0] == BaseRBlockType.OS_4:
# D7 D6 D5 O4 C3 C2 C1 C0 BT
dl = ctrl[0:4]
@@ -961,14 +971,18 @@ class BaseRSerdesSink:
# extract ordered sets
if os:
for k in [0, 4]:
if cl[k] and dl[k] == XgmiiCtrl.SEQ_OS:
self.os = int.from_bytes(db[k+1:k+4], 'big')
self.os_sig = False
self.log.info("RX sequence ordered set: 0x%06x", self.os)
elif cl[k] and dl[k] == XgmiiCtrl.SIG_OS:
self.os = int.from_bytes(db[k+1:k+4], 'big')
self.os_sig = True
self.log.info("RX signal ordered set: 0x%06x", self.os)
os_sig = dl[k] == XgmiiCtrl.SIG_OS
if cl[k] and (dl[k] == XgmiiCtrl.SEQ_OS or os_sig):
v = int.from_bytes(db[k+1:k+4], 'big')
if self.os == v and self.os_sig == os_sig:
self.os_match_cnt += 1
self.idle_match_cnt = 0
self.os = v
self.os_sig = os_sig
if os_sig:
self.log.info("RX signal ordered set: 0x%06x", self.os)
else:
self.log.info("RX sequence ordered set: 0x%06x", self.os)
for k in range(8):
d_val = dl[k]