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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-01-10 00:35:42 -08:00
parent be40d3ac2d
commit bedd85d7f6
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README.md
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@@ -74,6 +74,9 @@ To facilitate the dual-license model, contributions to the project can only be a
* DMA client for AXI stream * DMA client for AXI stream
* DMA interface for AXI * DMA interface for AXI
* DMA interface for UltraScale PCIe * DMA interface for UltraScale PCIe
* DMA descriptor mux
* DMA RAM demux
* DMA interface mux
* Segmented SDP RAM * Segmented SDP RAM
* Segmented dual-clock SDP RAM * Segmented dual-clock SDP RAM
* Ethernet * Ethernet
@@ -126,6 +129,7 @@ To facilitate the dual-license model, contributions to the project can only be a
* PCI Express * PCI Express
* PCIe AXI lite master * PCIe AXI lite master
* PCIe AXI lite master for Xilinx UltraScale * PCIe AXI lite master for Xilinx UltraScale
* MSI shim for Xilinx UltraScale
* Primitives * Primitives
* Arbiter * Arbiter
* Priority encoder * Priority encoder