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lss: Extract UART data width setting from interface

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-26 14:15:42 -08:00
parent 07d75f231a
commit c6cbb57fe7
4 changed files with 8 additions and 27 deletions
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13
rtl/lss/taxi_uart.sv
View File

@@ -15,10 +15,7 @@ Authors:
/*
* AXI4-Stream UART
*/
module taxi_uart #
(
parameter DATA_W = 8
)
module taxi_uart
(
input wire logic clk,
input wire logic rst,
@@ -54,9 +51,7 @@ module taxi_uart #
);
taxi_uart_tx #(
.DATA_W(DATA_W)
)
taxi_uart_tx
uart_tx_inst (
.clk(clk),
.rst(rst),
@@ -82,9 +77,7 @@ uart_tx_inst (
.prescale(prescale)
);
taxi_uart_rx #(
.DATA_W(DATA_W)
)
taxi_uart_rx
uart_rx_inst (
.clk(clk),
.rst(rst),

9
rtl/lss/taxi_uart_rx.sv
View File

@@ -15,10 +15,7 @@ Authors:
/*
* AXI4-Stream UART (RX)
*/
module taxi_uart_rx #
(
parameter DATA_W = 8
)
module taxi_uart_rx
(
input wire logic clk,
input wire logic rst,
@@ -47,9 +44,7 @@ module taxi_uart_rx #
);
// check configuration
if (m_axis_rx.DATA_W != DATA_W)
$fatal(0, "Error: Interface parameter DATA_W mismatch (instance %m)");
localparam DATA_W = m_axis_rx.DATA_W;
logic [DATA_W-1:0] m_axis_tdata_reg = 0;
logic m_axis_tvalid_reg = 0;

9
rtl/lss/taxi_uart_tx.sv
View File

@@ -15,10 +15,7 @@ Authors:
/*
* AXI4-Stream UART (TX)
*/
module taxi_uart_tx #
(
parameter DATA_W = 8
)
module taxi_uart_tx
(
input wire logic clk,
input wire logic rst,
@@ -44,9 +41,7 @@ module taxi_uart_tx #
input wire logic [15:0] prescale
);
// check configuration
if (s_axis_tx.DATA_W != DATA_W)
$fatal(0, "Error: Interface parameter DATA_W mismatch (instance %m)");
localparam DATA_W = s_axis_tx.DATA_W;
logic s_axis_tready_reg = 0;

4
tb/lss/taxi_uart/test_taxi_uart.sv
View File

@@ -39,9 +39,7 @@ logic rx_frame_error;
logic [15:0] prescale;
taxi_uart #(
.DATA_W(DATA_W)
)
taxi_uart
uut (
.clk(clk),
.rst(rst),