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lss: Extract UART data width setting from interface

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-26 14:15:42 -08:00
parent 07d75f231a
commit c6cbb57fe7
4 changed files with 8 additions and 27 deletions
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13
rtl/lss/taxi_uart.sv
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@@ -15,10 +15,7 @@ Authors:
/*
* AXI4-Stream UART
*/
module taxi_uart #
(
parameter DATA_W = 8
)
module taxi_uart
(
input wire logic clk,
input wire logic rst,
@@ -54,9 +51,7 @@ module taxi_uart #
);
taxi_uart_tx #(
.DATA_W(DATA_W)
)
taxi_uart_tx
uart_tx_inst (
.clk(clk),
.rst(rst),
@@ -82,9 +77,7 @@ uart_tx_inst (
.prescale(prescale)
);
taxi_uart_rx #(
.DATA_W(DATA_W)
)
taxi_uart_rx
uart_rx_inst (
.clk(clk),
.rst(rst),