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example/VCU118: Add example design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -123,6 +123,7 @@ Example designs are provided for several different FPGA boards, showcasing many
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* Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
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* Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
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* Xilinx Kria KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
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* Xilinx Kria KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)
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* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)
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* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
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* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
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39
example/VCU118/fpga/README.md
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39
example/VCU118/fpga/README.md
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@@ -0,0 +1,39 @@
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# Taxi Example Design for VCU118
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## Introduction
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This example design targets the Xilinx VCU118 FPGA board.
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The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a looped-back UART on on the USB UART connection.
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* USB UART
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* Looped-back UART
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* RJ-45 Ethernet port with TI DP83867ISRGZ PHY
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* Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
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* QSFP28
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* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA: xcvu9p-flga2104-2L-e
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* 1000BASE-T PHY: TI DP83867ISRGZ via SGMII
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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153
example/VCU118/fpga/common/vivado.mk
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153
example/VCU118/fpga/common/vivado.mk
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@@ -0,0 +1,153 @@
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# SPDX-License-Identifier: MIT
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016-2025 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - list of source files
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# INC_FILES - list of include files
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# XDC_FILES - list of timing constraint files
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# XCI_FILES - list of IP XCI files
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# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
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# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
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#
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# Note: both SYN_FILES and INC_FILES support file list files. File list
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# files are files with a .f extension that contain a list of additional
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# files to include, one path relative to the .f file location per line.
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# The .f files are processed recursively, and then the complete file list
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# is de-duplicated, with later files in the list taking precedence.
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include $(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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XDC_FILES ?= $(PROJECT).xdc
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
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INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
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###################################################################
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# Main Targets
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#
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# all: build everything (fpga)
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# fpga: build FPGA config
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# vivado: open project in Vivado
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# tmpclean: remove intermediate files
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# clean: remove output files and project files
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# distclean: remove archived output files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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# create fresh project if Makefile or IP files have changed
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create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
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for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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# source config TCL scripts if any source file has changed
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update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# output files (including potentially bit, bin, ltx, and xsa)
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
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977
example/VCU118/fpga/fpga.xdc
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977
example/VCU118/fpga/fpga.xdc
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@@ -0,0 +1,977 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx VCU118 board
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# part: xcvu9p-flga2104-2L-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# System clocks
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# 300 MHz
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
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#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
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# 250 MHz
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#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p]
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#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n]
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#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p]
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#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p]
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#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n]
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#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p]
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# 125 MHz
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set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# 90 MHz
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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# User SMA clock J34/J35
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#set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
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#set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
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#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
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# LEDs
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# DS7
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set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# DS6
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set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# DS8
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set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# DS9
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set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] ;# DS10
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set_property -dict {LOC AU37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] ;# DS12
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set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] ;# DS13
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set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] ;# DS18
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports {reset}] ;# SW5
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set_false_path -from [get_ports {reset}]
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set_input_delay 0 [get_ports {reset}]
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# Push buttons
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set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports {btnu}] ;# SW10
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set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports {btnl}] ;# SW6
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set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports {btnd}] ;# SW17
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set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports {btnr}] ;# SW9
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set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports {btnc}] ;# SW7
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||||||
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||||||
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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||||||
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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||||||
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||||||
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# DIP switches
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||||||
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set_property -dict {LOC B17 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] ;# SW12.1
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||||||
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set_property -dict {LOC G16 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] ;# SW12.2
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|
set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] ;# SW12.3
|
||||||
|
set_property -dict {LOC D21 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] ;# SW12.4
|
||||||
|
|
||||||
|
set_false_path -from [get_ports {sw[*]}]
|
||||||
|
set_input_delay 0 [get_ports {sw[*]}]
|
||||||
|
|
||||||
|
# PMOD0
|
||||||
|
#set_property -dict {LOC AY14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J52.1
|
||||||
|
#set_property -dict {LOC AY15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J52.3
|
||||||
|
#set_property -dict {LOC AW15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J52.5
|
||||||
|
#set_property -dict {LOC AV15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J52.7
|
||||||
|
#set_property -dict {LOC AV16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J52.2
|
||||||
|
#set_property -dict {LOC AU16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J52.4
|
||||||
|
#set_property -dict {LOC AT15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J52.6
|
||||||
|
#set_property -dict {LOC AT16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J52.8
|
||||||
|
|
||||||
|
#set_false_path -to [get_ports {pmod0[*]}]
|
||||||
|
#set_output_delay 0 [get_ports {pmod0[*]}]
|
||||||
|
|
||||||
|
# PMOD1
|
||||||
|
#set_property -dict {LOC N28 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J53.1
|
||||||
|
#set_property -dict {LOC M30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J53.3
|
||||||
|
#set_property -dict {LOC N30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J53.5
|
||||||
|
#set_property -dict {LOC P30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J53.7
|
||||||
|
#set_property -dict {LOC P29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J53.2
|
||||||
|
#set_property -dict {LOC L31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J53.4
|
||||||
|
#set_property -dict {LOC M31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J53.6
|
||||||
|
#set_property -dict {LOC R29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J53.8
|
||||||
|
|
||||||
|
#set_false_path -to [get_ports {pmod1[*]}]
|
||||||
|
#set_output_delay 0 [get_ports {pmod1[*]}]
|
||||||
|
|
||||||
|
# UART
|
||||||
|
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}]
|
||||||
|
set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}]
|
||||||
|
set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rts}]
|
||||||
|
set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {uart_cts}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {uart_txd uart_rts}]
|
||||||
|
set_output_delay 0 [get_ports {uart_txd uart_rts}]
|
||||||
|
set_false_path -from [get_ports {uart_rxd uart_cts}]
|
||||||
|
set_input_delay 0 [get_ports {uart_rxd uart_cts}]
|
||||||
|
|
||||||
|
# Gigabit Ethernet SGMII PHY
|
||||||
|
set_property -dict {LOC AU24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {phy_sgmii_rx_p}]
|
||||||
|
set_property -dict {LOC AV24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {phy_sgmii_rx_n}]
|
||||||
|
set_property -dict {LOC AU21 IOSTANDARD LVDS} [get_ports {phy_sgmii_tx_p}]
|
||||||
|
set_property -dict {LOC AV21 IOSTANDARD LVDS} [get_ports {phy_sgmii_tx_n}]
|
||||||
|
set_property -dict {LOC AT22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {phy_sgmii_clk_p}]
|
||||||
|
set_property -dict {LOC AU22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {phy_sgmii_clk_n}]
|
||||||
|
set_property -dict {LOC BA21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {phy_reset_n}]
|
||||||
|
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports {phy_int_n}]
|
||||||
|
set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {phy_mdio}]
|
||||||
|
set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {phy_mdc}]
|
||||||
|
|
||||||
|
# 625 MHz ref clock from SGMII PHY
|
||||||
|
#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {phy_reset_n phy_mdio phy_mdc}]
|
||||||
|
set_output_delay 0 [get_ports {phy_reset_n phy_mdio phy_mdc}]
|
||||||
|
set_false_path -from [get_ports {phy_int_n phy_mdio}]
|
||||||
|
set_input_delay 0 [get_ports {phy_int_n phy_mdio}]
|
||||||
|
|
||||||
|
# QSFP28 Interfaces
|
||||||
|
set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||||
|
set_property -dict {LOC W9 } [get_ports {qsfp1_mgt_refclk_0_p}] ;# MGTREFCLK0P_231 from U38.4
|
||||||
|
set_property -dict {LOC W8 } [get_ports {qsfp1_mgt_refclk_0_n}] ;# MGTREFCLK0N_231 from U38.5
|
||||||
|
#set_property -dict {LOC U9 } [get_ports {qsfp1_mgt_refclk_1_p}] ;# MGTREFCLK1P_231 from U57.28
|
||||||
|
#set_property -dict {LOC U8 } [get_ports {qsfp1_mgt_refclk_1_n}] ;# MGTREFCLK1N_231 from U57.29
|
||||||
|
#set_property -dict {LOC AM23 IOSTANDARD LVDS} [get_ports {qsfp1_recclk_p}] ;# to U57.16
|
||||||
|
#set_property -dict {LOC AM22 IOSTANDARD LVDS} [get_ports {qsfp1_recclk_n}] ;# to U57.17
|
||||||
|
set_property -dict {LOC AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp1_modsell}]
|
||||||
|
set_property -dict {LOC BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp1_resetl}]
|
||||||
|
set_property -dict {LOC AL21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {qsfp1_modprsl}]
|
||||||
|
set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {qsfp1_intl}]
|
||||||
|
set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp1_lpmode}]
|
||||||
|
|
||||||
|
# 156.25 MHz MGT reference clock
|
||||||
|
create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports {qsfp1_mgt_refclk_0_p}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||||
|
|
||||||
|
set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||||
|
set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||||
|
#set_property -dict {LOC R9 } [get_ports {qsfp2_mgt_refclk_0_p}] ;# MGTREFCLK0P_232 from U32.4 via U104.13
|
||||||
|
#set_property -dict {LOC R8 } [get_ports {qsfp2_mgt_refclk_0_n}] ;# MGTREFCLK0N_232 from U32.5 via U104.14
|
||||||
|
#set_property -dict {LOC N9 } [get_ports {qsfp2_mgt_refclk_1_p}] ;# MGTREFCLK1P_232 from U57.35
|
||||||
|
#set_property -dict {LOC N8 } [get_ports {qsfp2_mgt_refclk_1_n}] ;# MGTREFCLK1N_232 from U57.34
|
||||||
|
#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports {qsfp2_recclk_p}] ;# to U57.12
|
||||||
|
#set_property -dict {LOC AP22 IOSTANDARD LVDS} [get_ports {qsfp2_recclk_n}] ;# to U57.13
|
||||||
|
set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp2_modsell}]
|
||||||
|
set_property -dict {LOC AY22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp2_resetl}]
|
||||||
|
set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {qsfp2_modprsl}]
|
||||||
|
set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {qsfp2_intl}]
|
||||||
|
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp2_lpmode}]
|
||||||
|
|
||||||
|
# 156.25 MHz MGT reference clock
|
||||||
|
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports {qsfp2_mgt_refclk_0_p}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||||
|
|
||||||
|
# I2C interface
|
||||||
|
set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {i2c_scl}]
|
||||||
|
set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {i2c_sda}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {i2c_sda i2c_scl}]
|
||||||
|
set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||||
|
set_false_path -from [get_ports {i2c_sda i2c_scl}]
|
||||||
|
set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||||
|
|
||||||
|
# PCIe Interface
|
||||||
|
#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||||
|
#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||||
|
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||||
|
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||||
|
#set_property -dict {LOC AC9 } [get_ports {pcie_refclk_1_p}] ;# MGTREFCLK0P_227
|
||||||
|
#set_property -dict {LOC AC8 } [get_ports {pcie_refclk_1_n}] ;# MGTREFCLK0N_227
|
||||||
|
#set_property -dict {LOC AL9 } [get_ports {pcie_refclk_2_p}] ;# MGTREFCLK0P_225
|
||||||
|
#set_property -dict {LOC AL8 } [get_ports {pcie_refclk_2_n}] ;# MGTREFCLK0N_225
|
||||||
|
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||||
|
|
||||||
|
# 100 MHz MGT reference clock
|
||||||
|
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_1_p}]
|
||||||
|
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports {pcie_refclk_2_p}]
|
||||||
|
|
||||||
|
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||||
|
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||||
|
|
||||||
|
# FMC+ HSPC J22
|
||||||
|
#set_property -dict {LOC AL35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[0]}] ;# J22.G9 LA00_P_CC
|
||||||
|
#set_property -dict {LOC AL36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[0]}] ;# J22.G10 LA00_N_CC
|
||||||
|
#set_property -dict {LOC AL30 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[1]}] ;# J22.D8 LA01_P_CC
|
||||||
|
#set_property -dict {LOC AL31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[1]}] ;# J22.D9 LA01_N_CC
|
||||||
|
#set_property -dict {LOC AJ32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[2]}] ;# J22.H7 LA02_P
|
||||||
|
#set_property -dict {LOC AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[2]}] ;# J22.H8 LA02_N
|
||||||
|
#set_property -dict {LOC AT39 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[3]}] ;# J22.G12 LA03_P
|
||||||
|
#set_property -dict {LOC AT40 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[3]}] ;# J22.G13 LA03_N
|
||||||
|
#set_property -dict {LOC AR37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[4]}] ;# J22.H10 LA04_P
|
||||||
|
#set_property -dict {LOC AT37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[4]}] ;# J22.H11 LA04_N
|
||||||
|
#set_property -dict {LOC AP38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[5]}] ;# J22.D11 LA05_P
|
||||||
|
#set_property -dict {LOC AR38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[5]}] ;# J22.D12 LA05_N
|
||||||
|
#set_property -dict {LOC AT35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[6]}] ;# J22.C10 LA06_P
|
||||||
|
#set_property -dict {LOC AT36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[6]}] ;# J22.C11 LA06_N
|
||||||
|
#set_property -dict {LOC AP36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[7]}] ;# J22.H13 LA07_P
|
||||||
|
#set_property -dict {LOC AP37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[7]}] ;# J22.H14 LA07_N
|
||||||
|
#set_property -dict {LOC AK29 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[8]}] ;# J22.G12 LA08_P
|
||||||
|
#set_property -dict {LOC AK30 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[8]}] ;# J22.G13 LA08_N
|
||||||
|
#set_property -dict {LOC AJ33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[9]}] ;# J22.D14 LA09_P
|
||||||
|
#set_property -dict {LOC AK33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[9]}] ;# J22.D15 LA09_N
|
||||||
|
#set_property -dict {LOC AP35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[10]}] ;# J22.C14 LA10_P
|
||||||
|
#set_property -dict {LOC AR35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[10]}] ;# J22.C15 LA10_N
|
||||||
|
#set_property -dict {LOC AJ30 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[11]}] ;# J22.H16 LA11_P
|
||||||
|
#set_property -dict {LOC AJ31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[11]}] ;# J22.H17 LA11_N
|
||||||
|
#set_property -dict {LOC AH33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[12]}] ;# J22.G15 LA12_P
|
||||||
|
#set_property -dict {LOC AH34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[12]}] ;# J22.G16 LA12_N
|
||||||
|
#set_property -dict {LOC AJ35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[13]}] ;# J22.D17 LA13_P
|
||||||
|
#set_property -dict {LOC AJ36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[13]}] ;# J22.D18 LA13_N
|
||||||
|
#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[14]}] ;# J22.C18 LA14_P
|
||||||
|
#set_property -dict {LOC AH31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[14]}] ;# J22.C19 LA14_N
|
||||||
|
#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[15]}] ;# J22.H19 LA15_P
|
||||||
|
#set_property -dict {LOC AG33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[15]}] ;# J22.H20 LA15_N
|
||||||
|
#set_property -dict {LOC AG34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[16]}] ;# J22.G18 LA16_P
|
||||||
|
#set_property -dict {LOC AH35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[16]}] ;# J22.G19 LA16_N
|
||||||
|
#set_property -dict {LOC R34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[17]}] ;# J22.D20 LA17_P_CC
|
||||||
|
#set_property -dict {LOC P34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[17]}] ;# J22.D21 LA17_N_CC
|
||||||
|
#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[18]}] ;# J22.C22 LA18_P_CC
|
||||||
|
#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[18]}] ;# J22.C23 LA18_N_CC
|
||||||
|
#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[19]}] ;# J22.H22 LA19_P
|
||||||
|
#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[19]}] ;# J22.H23 LA19_N
|
||||||
|
#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[20]}] ;# J22.G21 LA20_P
|
||||||
|
#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[20]}] ;# J22.G22 LA20_N
|
||||||
|
#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[21]}] ;# J22.H25 LA21_P
|
||||||
|
#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[21]}] ;# J22.H26 LA21_N
|
||||||
|
#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[22]}] ;# J22.G24 LA22_P
|
||||||
|
#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[22]}] ;# J22.G25 LA22_N
|
||||||
|
#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[23]}] ;# J22.D23 LA23_P
|
||||||
|
#set_property -dict {LOC W32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[23]}] ;# J22.D24 LA23_N
|
||||||
|
#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[24]}] ;# J22.H28 LA24_P
|
||||||
|
#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[24]}] ;# J22.H29 LA24_N
|
||||||
|
#set_property -dict {LOC Y34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[25]}] ;# J22.G27 LA25_P
|
||||||
|
#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[25]}] ;# J22.G28 LA25_N
|
||||||
|
#set_property -dict {LOC V32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[26]}] ;# J22.D26 LA26_P
|
||||||
|
#set_property -dict {LOC U33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[26]}] ;# J22.D27 LA26_N
|
||||||
|
#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[27]}] ;# J22.C26 LA27_P
|
||||||
|
#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[27]}] ;# J22.C27 LA27_N
|
||||||
|
#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[28]}] ;# J22.H31 LA28_P
|
||||||
|
#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[28]}] ;# J22.H32 LA28_N
|
||||||
|
#set_property -dict {LOC U35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[29]}] ;# J22.G30 LA29_P
|
||||||
|
#set_property -dict {LOC T36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[29]}] ;# J22.G31 LA29_N
|
||||||
|
#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[30]}] ;# J22.H34 LA30_P
|
||||||
|
#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[30]}] ;# J22.H35 LA30_N
|
||||||
|
#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[31]}] ;# J22.G33 LA31_P
|
||||||
|
#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[31]}] ;# J22.G34 LA31_N
|
||||||
|
#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[32]}] ;# J22.H37 LA32_P
|
||||||
|
#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[32]}] ;# J22.H38 LA32_N
|
||||||
|
#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_p[33]}] ;# J22.G36 LA33_P
|
||||||
|
#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_la_n[33]}] ;# J22.G37 LA33_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[0]}] ;# J22.F4 HA00_P_CC
|
||||||
|
#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[0]}] ;# J22.F5 HA00_N_CC
|
||||||
|
#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[1]}] ;# J22.E2 HA01_P_CC
|
||||||
|
#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[1]}] ;# J22.E3 HA01_N_CC
|
||||||
|
#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[2]}] ;# J22.K7 HA02_P
|
||||||
|
#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[2]}] ;# J22.K8 HA02_N
|
||||||
|
#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[3]}] ;# J22.J6 HA03_P
|
||||||
|
#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[3]}] ;# J22.J7 HA03_N
|
||||||
|
#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[4]}] ;# J22.F7 HA04_P
|
||||||
|
#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[4]}] ;# J22.F8 HA04_N
|
||||||
|
#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[5]}] ;# J22.E6 HA05_P
|
||||||
|
#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[5]}] ;# J22.E7 HA05_N
|
||||||
|
#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[6]}] ;# J22.K10 HA06_P
|
||||||
|
#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[6]}] ;# J22.K11 HA06_N
|
||||||
|
#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[7]}] ;# J22.J9 HA07_P
|
||||||
|
#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[7]}] ;# J22.J10 HA07_N
|
||||||
|
#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[8]}] ;# J22.F10 HA08_P
|
||||||
|
#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[8]}] ;# J22.F11 HA08_N
|
||||||
|
#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[9]}] ;# J22.E9 HA09_P
|
||||||
|
#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[9]}] ;# J22.E10 HA09_N
|
||||||
|
#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[10]}] ;# J22.K13 HA10_P
|
||||||
|
#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[10]}] ;# J22.K14 HA10_N
|
||||||
|
#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[11]}] ;# J22.J12 HA11_P
|
||||||
|
#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[11]}] ;# J22.J13 HA11_N
|
||||||
|
#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[12]}] ;# J22.F13 HA12_P
|
||||||
|
#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[12]}] ;# J22.F14 HA12_N
|
||||||
|
#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[13]}] ;# J22.E12 HA13_P
|
||||||
|
#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[13]}] ;# J22.E13 HA13_N
|
||||||
|
#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[14]}] ;# J22.J15 HA14_P
|
||||||
|
#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[14]}] ;# J22.J16 HA14_N
|
||||||
|
#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[15]}] ;# J22.F14 HA15_P
|
||||||
|
#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[15]}] ;# J22.F16 HA15_N
|
||||||
|
#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[16]}] ;# J22.E15 HA16_P
|
||||||
|
#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[16]}] ;# J22.E16 HA16_N
|
||||||
|
#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[17]}] ;# J22.K16 HA17_P_CC
|
||||||
|
#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[17]}] ;# J22.K17 HA17_N_CC
|
||||||
|
#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[18]}] ;# J22.J18 HA18_P_CC
|
||||||
|
#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[18]}] ;# J22.J19 HA18_N_CC
|
||||||
|
#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[19]}] ;# J22.F19 HA19_P
|
||||||
|
#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[19]}] ;# J22.F20 HA19_N
|
||||||
|
#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[20]}] ;# J22.E18 HA20_P
|
||||||
|
#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[20]}] ;# J22.E19 HA20_N
|
||||||
|
#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[21]}] ;# J22.K19 HA21_P
|
||||||
|
#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[21]}] ;# J22.K20 HA21_N
|
||||||
|
#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[22]}] ;# J22.J21 HA22_P
|
||||||
|
#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[22]}] ;# J22.J22 HA22_N
|
||||||
|
#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_p[23]}] ;# J22.K22 HA23_P
|
||||||
|
#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_ha_n[23]}] ;# J22.K23 HA23_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_clk0_m2c_p}] ;# J22.H4 CLK0_M2C_P
|
||||||
|
#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_clk0_m2c_n}] ;# J22.H5 CLK0_M2C_N
|
||||||
|
#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_clk1_m2c_p}] ;# J22.G2 CLK1_M2C_P
|
||||||
|
#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_clk1_m2c_n}] ;# J22.G3 CLK1_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC AN33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_p}] ;# J22.L20 REFCLK_C2M_P
|
||||||
|
#set_property -dict {LOC AP33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_n}] ;# J22.L21 REFCLK_C2M_N
|
||||||
|
#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_refclk_m2c_p}] ;# J22.L24 REFCLK_M2C_P
|
||||||
|
#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_refclk_m2c_n}] ;# J22.L25 REFCLK_M2C_N
|
||||||
|
#set_property -dict {LOC AN34 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_p}] ;# J22.L16 SYNC_C2M_P
|
||||||
|
#set_property -dict {LOC AN35 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_n}] ;# J22.L17 SYNC_C2M_N
|
||||||
|
#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_sync_m2c_p}] ;# J22.L28 SYNC_M2C_P
|
||||||
|
#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmcp_hspc_sync_m2c_n}] ;# J22.L29 SYNC_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_pg_m2c}] ;# J22.F1 PG_M2C
|
||||||
|
#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_h_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L
|
||||||
|
#set_property -dict {LOC AM29 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_z_prsnt_m2c_l}] ;# J22.Z1 HSPC_PRSNT_M2C_L
|
||||||
|
|
||||||
|
#set_property -dict {LOC AT42} [get_ports {fmcp_hspc_dp_c2m_p[0]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C2 DP0_C2M_P
|
||||||
|
#set_property -dict {LOC AT43} [get_ports {fmcp_hspc_dp_c2m_n[0]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C3 DP0_C2M_N
|
||||||
|
#set_property -dict {LOC AR45} [get_ports {fmcp_hspc_dp_m2c_p[0]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C6 DP0_M2C_P
|
||||||
|
#set_property -dict {LOC AR46} [get_ports {fmcp_hspc_dp_m2c_n[0]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C7 DP0_M2C_N
|
||||||
|
#set_property -dict {LOC AP42} [get_ports {fmcp_hspc_dp_c2m_p[1]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A22 DP1_C2M_P
|
||||||
|
#set_property -dict {LOC AP43} [get_ports {fmcp_hspc_dp_c2m_n[1]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A23 DP1_C2M_N
|
||||||
|
#set_property -dict {LOC AN45} [get_ports {fmcp_hspc_dp_m2c_p[1]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A2 DP1_M2C_P
|
||||||
|
#set_property -dict {LOC AN46} [get_ports {fmcp_hspc_dp_m2c_n[1]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A3 DP1_M2C_N
|
||||||
|
#set_property -dict {LOC AM42} [get_ports {fmcp_hspc_dp_c2m_p[2]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A26 DP2_C2M_P
|
||||||
|
#set_property -dict {LOC AM43} [get_ports {fmcp_hspc_dp_c2m_n[2]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A27 DP2_C2M_N
|
||||||
|
#set_property -dict {LOC AL45} [get_ports {fmcp_hspc_dp_m2c_p[2]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A6 DP2_M2C_P
|
||||||
|
#set_property -dict {LOC AL46} [get_ports {fmcp_hspc_dp_m2c_n[2]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A7 DP2_M2C_N
|
||||||
|
#set_property -dict {LOC AL40} [get_ports {fmcp_hspc_dp_c2m_p[3]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A30 DP3_C2M_P
|
||||||
|
#set_property -dict {LOC AL41} [get_ports {fmcp_hspc_dp_c2m_n[3]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A31 DP3_C2M_N
|
||||||
|
#set_property -dict {LOC AJ45} [get_ports {fmcp_hspc_dp_m2c_p[3]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A10 DP3_M2C_P
|
||||||
|
#set_property -dict {LOC AJ46} [get_ports {fmcp_hspc_dp_m2c_n[3]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A11 DP3_M2C_N
|
||||||
|
#set_property -dict {LOC AK38} [get_ports {fmcp_hspc_mgt_refclk_0_0_p}] ;# MGTREFCLK0P_121 from U40.1 Q0 from J22.D4 GBTCLK0_M2C_P
|
||||||
|
#set_property -dict {LOC AK39} [get_ports {fmcp_hspc_mgt_refclk_0_0_n}] ;# MGTREFCLK0N_121 from U40.2 NQ0 from J22.D5 GBTCLK0_M2C_N
|
||||||
|
#set_property -dict {LOC AH38} [get_ports {fmcp_hspc_mgt_refclk_0_1_p}] ;# MGTREFCLK1P_121 from U39.5 Q0_P from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AH39} [get_ports {fmcp_hspc_mgt_refclk_0_1_n}] ;# MGTREFCLK1N_121 from U39.6 Q0_N from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_0 [get_ports {fmcp_hspc_mgt_refclk_0_0_p}]
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_1 [get_ports {fmcp_hspc_mgt_refclk_0_1_p}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC T42 } [get_ports {fmcp_hspc_dp_c2m_p[4]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A34 DP4_C2M_P
|
||||||
|
#set_property -dict {LOC T43 } [get_ports {fmcp_hspc_dp_c2m_n[4]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A35 DP4_C2M_N
|
||||||
|
#set_property -dict {LOC W45 } [get_ports {fmcp_hspc_dp_m2c_p[4]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A14 DP4_M2C_P
|
||||||
|
#set_property -dict {LOC W46 } [get_ports {fmcp_hspc_dp_m2c_n[4]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A15 DP4_M2C_N
|
||||||
|
#set_property -dict {LOC P42 } [get_ports {fmcp_hspc_dp_c2m_p[5]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A38 DP5_C2M_P
|
||||||
|
#set_property -dict {LOC P43 } [get_ports {fmcp_hspc_dp_c2m_n[5]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A39 DP5_C2M_N
|
||||||
|
#set_property -dict {LOC U45 } [get_ports {fmcp_hspc_dp_m2c_p[5]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A18 DP5_M2C_P
|
||||||
|
#set_property -dict {LOC U46 } [get_ports {fmcp_hspc_dp_m2c_n[5]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A19 DP5_M2C_N
|
||||||
|
#set_property -dict {LOC M42 } [get_ports {fmcp_hspc_dp_c2m_p[6]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B36 DP6_C2M_P
|
||||||
|
#set_property -dict {LOC M43 } [get_ports {fmcp_hspc_dp_c2m_n[6]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B37 DP6_C2M_N
|
||||||
|
#set_property -dict {LOC R45 } [get_ports {fmcp_hspc_dp_m2c_p[6]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B16 DP6_M2C_P
|
||||||
|
#set_property -dict {LOC R46 } [get_ports {fmcp_hspc_dp_m2c_n[6]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B17 DP6_M2C_N
|
||||||
|
#set_property -dict {LOC K42 } [get_ports {fmcp_hspc_dp_c2m_p[7]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B32 DP7_C2M_P
|
||||||
|
#set_property -dict {LOC K43 } [get_ports {fmcp_hspc_dp_c2m_n[7]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B33 DP7_C2M_N
|
||||||
|
#set_property -dict {LOC N45 } [get_ports {fmcp_hspc_dp_m2c_p[7]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B12 DP7_M2C_P
|
||||||
|
#set_property -dict {LOC N46 } [get_ports {fmcp_hspc_dp_m2c_n[7]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B13 DP7_M2C_N
|
||||||
|
#set_property -dict {LOC V38 } [get_ports {fmcp_hspc_mgt_refclk_1_0_p}] ;# MGTREFCLK0P_126 from U40.3 Q1 from J22.D4 GBTCLK0_M2C_P
|
||||||
|
#set_property -dict {LOC V39 } [get_ports {fmcp_hspc_mgt_refclk_1_0_n}] ;# MGTREFCLK0N_126 from U40.4 NQ1 from J22.D5 GBTCLK0_M2C_N
|
||||||
|
#set_property -dict {LOC T38 } [get_ports {fmcp_hspc_mgt_refclk_1_1_p}] ;# MGTREFCLK1P_126 from U39.8 Q1_P from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC T39 } [get_ports {fmcp_hspc_mgt_refclk_1_1_n}] ;# MGTREFCLK1N_126 from U39.9 Q1_N from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_0 [get_ports {fmcp_hspc_mgt_refclk_1_0_p}]
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_1 [get_ports {fmcp_hspc_mgt_refclk_1_1_p}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC AK42} [get_ports {fmcp_hspc_dp_c2m_p[8]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B28 DP8_C2M_P
|
||||||
|
#set_property -dict {LOC AK43} [get_ports {fmcp_hspc_dp_c2m_n[8]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B29 DP8_C2M_N
|
||||||
|
#set_property -dict {LOC AG45} [get_ports {fmcp_hspc_dp_m2c_p[8]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B8 DP8_M2C_P
|
||||||
|
#set_property -dict {LOC AG46} [get_ports {fmcp_hspc_dp_m2c_n[8]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B9 DP8_M2C_N
|
||||||
|
#set_property -dict {LOC AJ40} [get_ports {fmcp_hspc_dp_c2m_p[9]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B24 DP9_C2M_P
|
||||||
|
#set_property -dict {LOC AJ41} [get_ports {fmcp_hspc_dp_c2m_n[9]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B25 DP9_C2M_N
|
||||||
|
#set_property -dict {LOC AF43} [get_ports {fmcp_hspc_dp_m2c_p[9]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B4 DP9_M2C_P
|
||||||
|
#set_property -dict {LOC AF44} [get_ports {fmcp_hspc_dp_m2c_n[9]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B5 DP9_M2C_N
|
||||||
|
#set_property -dict {LOC AG40} [get_ports {fmcp_hspc_dp_c2m_p[10]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z24 DP10_C2M_P
|
||||||
|
#set_property -dict {LOC AG41} [get_ports {fmcp_hspc_dp_c2m_n[10]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z25 DP10_C2M_N
|
||||||
|
#set_property -dict {LOC AE45} [get_ports {fmcp_hspc_dp_m2c_p[10]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y10 DP10_M2C_P
|
||||||
|
#set_property -dict {LOC AE46} [get_ports {fmcp_hspc_dp_m2c_n[10]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y11 DP10_M2C_N
|
||||||
|
#set_property -dict {LOC AE40} [get_ports {fmcp_hspc_dp_c2m_p[11]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y26 DP11_C2M_P
|
||||||
|
#set_property -dict {LOC AE41} [get_ports {fmcp_hspc_dp_c2m_n[11]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y27 DP11_C2M_N
|
||||||
|
#set_property -dict {LOC AD43} [get_ports {fmcp_hspc_dp_m2c_p[11]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z12 DP11_M2C_P
|
||||||
|
#set_property -dict {LOC AD44} [get_ports {fmcp_hspc_dp_m2c_n[11]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z13 DP11_M2C_N
|
||||||
|
#set_property -dict {LOC AF38} [get_ports {fmcp_hspc_mgt_refclk_2_0_p}] ;# MGTREFCLK0P_122 from J22.L12 GBTCLK2_M2C_P
|
||||||
|
#set_property -dict {LOC AF39} [get_ports {fmcp_hspc_mgt_refclk_2_0_n}] ;# MGTREFCLK0N_122 from J22.L13 GBTCLK2_M2C_N
|
||||||
|
#set_property -dict {LOC AD38} [get_ports {fmcp_hspc_mgt_refclk_2_1_p}] ;# MGTREFCLK1P_122 from U39.11 Q2_P from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AD39} [get_ports {fmcp_hspc_mgt_refclk_2_1_n}] ;# MGTREFCLK1N_122 from U39.12 Q2_N from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_0 [get_ports {fmcp_hspc_mgt_refclk_2_0_p}]
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_1 [get_ports {fmcp_hspc_mgt_refclk_2_1_p}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC AC40} [get_ports {fmcp_hspc_dp_c2m_p[12]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z28 DP12_C2M_P
|
||||||
|
#set_property -dict {LOC AC41} [get_ports {fmcp_hspc_dp_c2m_n[12]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z29 DP12_C2M_N
|
||||||
|
#set_property -dict {LOC AC45} [get_ports {fmcp_hspc_dp_m2c_p[12]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y14 DP12_M2C_P
|
||||||
|
#set_property -dict {LOC AC46} [get_ports {fmcp_hspc_dp_m2c_n[12]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y15 DP12_M2C_N
|
||||||
|
#set_property -dict {LOC AA40} [get_ports {fmcp_hspc_dp_c2m_p[13]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y30 DP13_C2M_P
|
||||||
|
#set_property -dict {LOC AA41} [get_ports {fmcp_hspc_dp_c2m_n[13]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y31 DP13_C2M_N
|
||||||
|
#set_property -dict {LOC AB43} [get_ports {fmcp_hspc_dp_m2c_p[13]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z16 DP13_M2C_P
|
||||||
|
#set_property -dict {LOC AB44} [get_ports {fmcp_hspc_dp_m2c_n[13]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z17 DP13_M2C_N
|
||||||
|
#set_property -dict {LOC W40 } [get_ports {fmcp_hspc_dp_c2m_p[14]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M18 DP14_C2M_P
|
||||||
|
#set_property -dict {LOC W41 } [get_ports {fmcp_hspc_dp_c2m_n[14]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M19 DP14_C2M_N
|
||||||
|
#set_property -dict {LOC AA45} [get_ports {fmcp_hspc_dp_m2c_p[14]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y18 DP14_M2C_P
|
||||||
|
#set_property -dict {LOC AA46} [get_ports {fmcp_hspc_dp_m2c_n[14]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y19 DP14_M2C_N
|
||||||
|
#set_property -dict {LOC U40 } [get_ports {fmcp_hspc_dp_c2m_p[15]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M22 DP15_C2M_P
|
||||||
|
#set_property -dict {LOC U41 } [get_ports {fmcp_hspc_dp_c2m_n[15]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M23 DP15_C2M_N
|
||||||
|
#set_property -dict {LOC Y43 } [get_ports {fmcp_hspc_dp_m2c_p[15]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y22 DP15_M2C_P
|
||||||
|
#set_property -dict {LOC Y44 } [get_ports {fmcp_hspc_dp_m2c_n[15]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y23 DP15_M2C_N
|
||||||
|
#set_property -dict {LOC AB38} [get_ports {fmcp_hspc_mgt_refclk_3_0_p}] ;# MGTREFCLK0P_125 from J22.L8 GBTCLK3_M2C_P
|
||||||
|
#set_property -dict {LOC AB39} [get_ports {fmcp_hspc_mgt_refclk_3_0_n}] ;# MGTREFCLK0N_125 from J22.L9 GBTCLK3_M2C_N
|
||||||
|
#set_property -dict {LOC Y38 } [get_ports {fmcp_hspc_mgt_refclk_3_1_p}] ;# MGTREFCLK1P_125 from U39.13 Q3_P from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC Y39 } [get_ports {fmcp_hspc_mgt_refclk_3_1_n}] ;# MGTREFCLK1N_125 from U39.14 Q3_N from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_0 [get_ports {fmcp_hspc_mgt_refclk_3_0_p}]
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_1 [get_ports {fmcp_hspc_mgt_refclk_3_1_p}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC H42 } [get_ports {fmcp_hspc_dp_c2m_p[16]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M26 DP16_C2M_P
|
||||||
|
#set_property -dict {LOC H43 } [get_ports {fmcp_hspc_dp_c2m_n[16]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M27 DP16_C2M_N
|
||||||
|
#set_property -dict {LOC L45 } [get_ports {fmcp_hspc_dp_m2c_p[16]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z32 DP16_M2C_P
|
||||||
|
#set_property -dict {LOC L46 } [get_ports {fmcp_hspc_dp_m2c_n[16]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z33 DP16_M2C_N
|
||||||
|
#set_property -dict {LOC F42 } [get_ports {fmcp_hspc_dp_c2m_p[17]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M30 DP17_C2M_P
|
||||||
|
#set_property -dict {LOC F43 } [get_ports {fmcp_hspc_dp_c2m_n[17]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M31 DP17_C2M_N
|
||||||
|
#set_property -dict {LOC J45 } [get_ports {fmcp_hspc_dp_m2c_p[17]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y34 DP17_M2C_P
|
||||||
|
#set_property -dict {LOC J46 } [get_ports {fmcp_hspc_dp_m2c_n[17]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y35 DP17_M2C_N
|
||||||
|
#set_property -dict {LOC D42 } [get_ports {fmcp_hspc_dp_c2m_p[18]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M34 DP18_C2M_P
|
||||||
|
#set_property -dict {LOC D43 } [get_ports {fmcp_hspc_dp_c2m_n[18]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M35 DP18_C2M_N
|
||||||
|
#set_property -dict {LOC G45 } [get_ports {fmcp_hspc_dp_m2c_p[18]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z36 DP18_M2C_P
|
||||||
|
#set_property -dict {LOC G46 } [get_ports {fmcp_hspc_dp_m2c_n[18]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z37 DP18_M2C_N
|
||||||
|
#set_property -dict {LOC B42 } [get_ports {fmcp_hspc_dp_c2m_p[19]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M38 DP19_C2M_P
|
||||||
|
#set_property -dict {LOC B43 } [get_ports {fmcp_hspc_dp_c2m_n[19]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M39 DP19_C2M_N
|
||||||
|
#set_property -dict {LOC E45 } [get_ports {fmcp_hspc_dp_m2c_p[19]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y38 DP19_M2C_P
|
||||||
|
#set_property -dict {LOC E46 } [get_ports {fmcp_hspc_dp_m2c_n[19]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y39 DP19_M2C_N
|
||||||
|
#set_property -dict {LOC R40 } [get_ports {fmcp_hspc_mgt_refclk_4_0_p}] ;# MGTREFCLK0P_127 from J22.L4 GBTCLK4_M2C_P
|
||||||
|
#set_property -dict {LOC R41 } [get_ports {fmcp_hspc_mgt_refclk_4_0_n}] ;# MGTREFCLK0N_127 from J22.L5 GBTCLK4_M2C_N
|
||||||
|
#set_property -dict {LOC N40 } [get_ports {fmcp_hspc_mgt_refclk_4_1_p}] ;# MGTREFCLK1P_127 from U39.16 Q4_P from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC N41 } [get_ports {fmcp_hspc_mgt_refclk_4_1_n}] ;# MGTREFCLK1N_127 from U39.17 Q4_N from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_0 [get_ports {fmcp_hspc_mgt_refclk_4_0_p}]
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_1 [get_ports {fmcp_hspc_mgt_refclk_4_1_p}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC BD42} [get_ports {fmcp_hspc_dp_c2m_p[20]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z8 DP20_C2M_P
|
||||||
|
#set_property -dict {LOC BD43} [get_ports {fmcp_hspc_dp_c2m_n[20]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z9 DP20_C2M_N
|
||||||
|
#set_property -dict {LOC BC45} [get_ports {fmcp_hspc_dp_m2c_p[20]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M14 DP20_M2C_P
|
||||||
|
#set_property -dict {LOC BC46} [get_ports {fmcp_hspc_dp_m2c_n[20]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M15 DP20_M2C_N
|
||||||
|
#set_property -dict {LOC BB42} [get_ports {fmcp_hspc_dp_c2m_p[21]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y6 DP21_C2M_P
|
||||||
|
#set_property -dict {LOC BB43} [get_ports {fmcp_hspc_dp_c2m_n[21]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y7 DP21_C2M_N
|
||||||
|
#set_property -dict {LOC BA45} [get_ports {fmcp_hspc_dp_m2c_p[21]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M10 DP21_M2C_P
|
||||||
|
#set_property -dict {LOC BA46} [get_ports {fmcp_hspc_dp_m2c_n[21]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M11 DP21_M2C_N
|
||||||
|
#set_property -dict {LOC AY42} [get_ports {fmcp_hspc_dp_c2m_p[22]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z4 DP22_C2M_P
|
||||||
|
#set_property -dict {LOC AY43} [get_ports {fmcp_hspc_dp_c2m_n[22]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z5 DP22_C2M_N
|
||||||
|
#set_property -dict {LOC AW45} [get_ports {fmcp_hspc_dp_m2c_p[22]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M6 DP22_M2C_P
|
||||||
|
#set_property -dict {LOC AW46} [get_ports {fmcp_hspc_dp_m2c_n[22]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M7 DP22_M2C_N
|
||||||
|
#set_property -dict {LOC AV42} [get_ports {fmcp_hspc_dp_c2m_p[23]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y2 DP23_C2M_P
|
||||||
|
#set_property -dict {LOC AV43} [get_ports {fmcp_hspc_dp_c2m_n[23]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y3 DP23_C2M_N
|
||||||
|
#set_property -dict {LOC AU45} [get_ports {fmcp_hspc_dp_m2c_p[23]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M2 DP23_M2C_P
|
||||||
|
#set_property -dict {LOC AU46} [get_ports {fmcp_hspc_dp_m2c_n[23]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M3 DP23_M2C_N
|
||||||
|
#set_property -dict {LOC AN40} [get_ports {fmcp_hspc_mgt_refclk_5_0_p}] ;# MGTREFCLK0P_120 from J22.Z20 GBTCLK5_M2C_P
|
||||||
|
#set_property -dict {LOC AN41} [get_ports {fmcp_hspc_mgt_refclk_5_0_n}] ;# MGTREFCLK0N_120 from J22.Z21 GBTCLK5_M2C_N
|
||||||
|
#set_property -dict {LOC AM38} [get_ports {fmcp_hspc_mgt_refclk_5_1_p}] ;# MGTREFCLK1P_120 from U39.19 Q5_P from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AM39} [get_ports {fmcp_hspc_mgt_refclk_5_1_n}] ;# MGTREFCLK1N_120 from U39.20 Q5_N from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_0 [get_ports {fmcp_hspc_mgt_refclk_5_0_p}]
|
||||||
|
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_1 [get_ports {fmcp_hspc_mgt_refclk_5_1_p}]
|
||||||
|
|
||||||
|
# FMC HPC1 J2
|
||||||
|
#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[0]}] ;# J2.G9 LA00_P_CC
|
||||||
|
#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[0]}] ;# J2.G10 LA00_N_CC
|
||||||
|
#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[1]}] ;# J2.D8 LA01_P_CC
|
||||||
|
#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[1]}] ;# J2.D9 LA01_N_CC
|
||||||
|
#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[2]}] ;# J2.H7 LA02_P
|
||||||
|
#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[2]}] ;# J2.H8 LA02_N
|
||||||
|
#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[3]}] ;# J2.G12 LA03_P
|
||||||
|
#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[3]}] ;# J2.G13 LA03_N
|
||||||
|
#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[4]}] ;# J2.H10 LA04_P
|
||||||
|
#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[4]}] ;# J2.H11 LA04_N
|
||||||
|
#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[5]}] ;# J2.D11 LA05_P
|
||||||
|
#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[5]}] ;# J2.D12 LA05_N
|
||||||
|
#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[6]}] ;# J2.C10 LA06_P
|
||||||
|
#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[6]}] ;# J2.C11 LA06_N
|
||||||
|
#set_property -dict {LOC BC15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[7]}] ;# J2.H13 LA07_P
|
||||||
|
#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[7]}] ;# J2.H14 LA07_N
|
||||||
|
#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[8]}] ;# J2.G12 LA08_P
|
||||||
|
#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[8]}] ;# J2.G13 LA08_N
|
||||||
|
#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[9]}] ;# J2.D14 LA09_P
|
||||||
|
#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[9]}] ;# J2.D15 LA09_N
|
||||||
|
#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[10]}] ;# J2.C14 LA10_P
|
||||||
|
#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[10]}] ;# J2.C15 LA10_N
|
||||||
|
#set_property -dict {LOC BA16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[11]}] ;# J2.H16 LA11_P
|
||||||
|
#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[11]}] ;# J2.H17 LA11_N
|
||||||
|
#set_property -dict {LOC BC14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[12]}] ;# J2.G15 LA12_P
|
||||||
|
#set_property -dict {LOC BC13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[12]}] ;# J2.G16 LA12_N
|
||||||
|
#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[13]}] ;# J2.D17 LA13_P
|
||||||
|
#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[13]}] ;# J2.D18 LA13_N
|
||||||
|
#set_property -dict {LOC AW8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[14]}] ;# J2.C18 LA14_P
|
||||||
|
#set_property -dict {LOC AW7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[14]}] ;# J2.C19 LA14_N
|
||||||
|
#set_property -dict {LOC BB16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[15]}] ;# J2.H19 LA15_P
|
||||||
|
#set_property -dict {LOC BC16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[15]}] ;# J2.H20 LA15_N
|
||||||
|
#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[16]}] ;# J2.G18 LA16_P
|
||||||
|
#set_property -dict {LOC AB8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[16]}] ;# J2.G19 LA16_N
|
||||||
|
#set_property -dict {LOC AR14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[17]}] ;# J2.D20 LA17_P_CC
|
||||||
|
#set_property -dict {LOC AT14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[17]}] ;# J2.D21 LA17_N_CC
|
||||||
|
#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[18]}] ;# J2.C22 LA18_P_CC
|
||||||
|
#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[18]}] ;# J2.C23 LA18_N_CC
|
||||||
|
#set_property -dict {LOC AW12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[19]}] ;# J2.H22 LA19_P
|
||||||
|
#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[19]}] ;# J2.H23 LA19_N
|
||||||
|
#set_property -dict {LOC AW11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[20]}] ;# J2.G21 LA20_P
|
||||||
|
#set_property -dict {LOC AY10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[20]}] ;# J2.G22 LA20_N
|
||||||
|
#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[21]}] ;# J2.H25 LA21_P
|
||||||
|
#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[21]}] ;# J2.H26 LA21_N
|
||||||
|
#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[22]}] ;# J2.G24 LA22_P
|
||||||
|
#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[22]}] ;# J2.G25 LA22_N
|
||||||
|
#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[23]}] ;# J2.D23 LA23_P
|
||||||
|
#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[23]}] ;# J2.D24 LA23_N
|
||||||
|
#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[24]}] ;# J2.H28 LA24_P
|
||||||
|
#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[24]}] ;# J2.H29 LA24_N
|
||||||
|
#set_property -dict {LOC AT12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[25]}] ;# J2.G27 LA25_P
|
||||||
|
#set_property -dict {LOC AU12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[25]}] ;# J2.G28 LA25_N
|
||||||
|
#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[26]}] ;# J2.D26 LA26_P
|
||||||
|
#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[26]}] ;# J2.D27 LA26_N
|
||||||
|
#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[27]}] ;# J2.C26 LA27_P
|
||||||
|
#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[27]}] ;# J2.C27 LA27_N
|
||||||
|
#set_property -dict {LOC AV10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[28]}] ;# J2.H31 LA28_P
|
||||||
|
#set_property -dict {LOC AW10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[28]}] ;# J2.H32 LA28_N
|
||||||
|
#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[29]}] ;# J2.G30 LA29_P
|
||||||
|
#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[29]}] ;# J2.G31 LA29_N
|
||||||
|
#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[30]}] ;# J2.H34 LA30_P
|
||||||
|
#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[30]}] ;# J2.H35 LA30_N
|
||||||
|
#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[31]}] ;# J2.G33 LA31_P
|
||||||
|
#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[31]}] ;# J2.G34 LA31_N
|
||||||
|
#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[32]}] ;# J2.H37 LA32_P
|
||||||
|
#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[32]}] ;# J2.H38 LA32_N
|
||||||
|
#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_p[33]}] ;# J2.G36 LA33_P
|
||||||
|
#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_la_n[33]}] ;# J2.G37 LA33_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC BC9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_clk0_m2c_p}] ;# J2.H4 CLK0_M2C_P
|
||||||
|
#set_property -dict {LOC BC8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_clk0_m2c_n}] ;# J2.H5 CLK0_M2C_N
|
||||||
|
#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_clk1_m2c_p}] ;# J2.G2 CLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_hpc1_clk1_m2c_n}] ;# J2.G3 CLK1_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC BA7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C
|
||||||
|
#set_property -dict {LOC BB7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L
|
||||||
|
|
||||||
|
# DDR4 C1
|
||||||
|
# 5x MT40A256M16GE-075E
|
||||||
|
#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||||
|
#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||||
|
#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||||
|
#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||||
|
#set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||||
|
#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||||
|
#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||||
|
#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||||
|
#set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||||
|
#set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||||
|
#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||||
|
#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||||
|
#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||||
|
#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||||
|
#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||||
|
#set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||||
|
#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||||
|
#set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||||
|
#set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||||
|
#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||||
|
#set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||||
|
#set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||||
|
#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||||
|
#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||||
|
#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||||
|
#set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||||
|
#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||||
|
#set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||||
|
#set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||||
|
#set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0
|
||||||
|
#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1
|
||||||
|
#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2
|
||||||
|
#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3
|
||||||
|
#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4
|
||||||
|
#set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5
|
||||||
|
#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6
|
||||||
|
#set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7
|
||||||
|
#set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0
|
||||||
|
#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1
|
||||||
|
#set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2
|
||||||
|
#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3
|
||||||
|
#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4
|
||||||
|
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5
|
||||||
|
#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6
|
||||||
|
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7
|
||||||
|
#set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0
|
||||||
|
#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1
|
||||||
|
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2
|
||||||
|
#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3
|
||||||
|
#set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4
|
||||||
|
#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5
|
||||||
|
#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6
|
||||||
|
#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7
|
||||||
|
#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0
|
||||||
|
#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1
|
||||||
|
#set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2
|
||||||
|
#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3
|
||||||
|
#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4
|
||||||
|
#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5
|
||||||
|
#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6
|
||||||
|
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7
|
||||||
|
#set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0
|
||||||
|
#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1
|
||||||
|
#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2
|
||||||
|
#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3
|
||||||
|
#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4
|
||||||
|
#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5
|
||||||
|
#set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6
|
||||||
|
#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7
|
||||||
|
#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0
|
||||||
|
#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1
|
||||||
|
#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2
|
||||||
|
#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3
|
||||||
|
#set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4
|
||||||
|
#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5
|
||||||
|
#set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6
|
||||||
|
#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7
|
||||||
|
#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0
|
||||||
|
#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1
|
||||||
|
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2
|
||||||
|
#set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3
|
||||||
|
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4
|
||||||
|
#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5
|
||||||
|
#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6
|
||||||
|
#set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7
|
||||||
|
#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0
|
||||||
|
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1
|
||||||
|
#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2
|
||||||
|
#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3
|
||||||
|
#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4
|
||||||
|
#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5
|
||||||
|
#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6
|
||||||
|
#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7
|
||||||
|
#set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0
|
||||||
|
#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1
|
||||||
|
#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2
|
||||||
|
#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3
|
||||||
|
#set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4
|
||||||
|
#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5
|
||||||
|
#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6
|
||||||
|
#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7
|
||||||
|
#set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0
|
||||||
|
#set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1
|
||||||
|
#set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2
|
||||||
|
#set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3
|
||||||
|
#set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4
|
||||||
|
#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5
|
||||||
|
#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6
|
||||||
|
#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7
|
||||||
|
#set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
# DDR4 C2
|
||||||
|
# 5x MT40A256M16GE-075E
|
||||||
|
#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||||
|
#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||||
|
#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||||
|
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||||
|
#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||||
|
#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||||
|
#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||||
|
#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||||
|
#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||||
|
#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||||
|
#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||||
|
#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||||
|
#set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||||
|
#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||||
|
#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||||
|
#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||||
|
#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||||
|
#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||||
|
#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||||
|
#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||||
|
#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}]
|
||||||
|
#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}]
|
||||||
|
#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}]
|
||||||
|
#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}]
|
||||||
|
#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||||
|
#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}]
|
||||||
|
#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||||
|
#set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||||
|
#set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}]
|
||||||
|
#set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0
|
||||||
|
#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1
|
||||||
|
#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2
|
||||||
|
#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3
|
||||||
|
#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4
|
||||||
|
#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5
|
||||||
|
#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6
|
||||||
|
#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7
|
||||||
|
#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0
|
||||||
|
#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1
|
||||||
|
#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2
|
||||||
|
#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3
|
||||||
|
#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4
|
||||||
|
#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5
|
||||||
|
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6
|
||||||
|
#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7
|
||||||
|
#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0
|
||||||
|
#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1
|
||||||
|
#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2
|
||||||
|
#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3
|
||||||
|
#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4
|
||||||
|
#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5
|
||||||
|
#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6
|
||||||
|
#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7
|
||||||
|
#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0
|
||||||
|
#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1
|
||||||
|
#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2
|
||||||
|
#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3
|
||||||
|
#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4
|
||||||
|
#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5
|
||||||
|
#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6
|
||||||
|
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7
|
||||||
|
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0
|
||||||
|
#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1
|
||||||
|
#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2
|
||||||
|
#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3
|
||||||
|
#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4
|
||||||
|
#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5
|
||||||
|
#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6
|
||||||
|
#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7
|
||||||
|
#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0
|
||||||
|
#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1
|
||||||
|
#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2
|
||||||
|
#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3
|
||||||
|
#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4
|
||||||
|
#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5
|
||||||
|
#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6
|
||||||
|
#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7
|
||||||
|
#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0
|
||||||
|
#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1
|
||||||
|
#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2
|
||||||
|
#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3
|
||||||
|
#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4
|
||||||
|
#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5
|
||||||
|
#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6
|
||||||
|
#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7
|
||||||
|
#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0
|
||||||
|
#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1
|
||||||
|
#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2
|
||||||
|
#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3
|
||||||
|
#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4
|
||||||
|
#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5
|
||||||
|
#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6
|
||||||
|
#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7
|
||||||
|
#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0
|
||||||
|
#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1
|
||||||
|
#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2
|
||||||
|
#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3
|
||||||
|
#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4
|
||||||
|
#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5
|
||||||
|
#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6
|
||||||
|
#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7
|
||||||
|
#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0
|
||||||
|
#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1
|
||||||
|
#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2
|
||||||
|
#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3
|
||||||
|
#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4
|
||||||
|
#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5
|
||||||
|
#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6
|
||||||
|
#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7
|
||||||
|
#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
# QSPI flash
|
||||||
|
#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||||
|
#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||||
|
#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
|
||||||
|
#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
|
||||||
|
#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
|
||||||
|
|
||||||
|
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||||
|
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||||
|
#set_false_path -from [get_ports {qspi_1_dq}]
|
||||||
|
#set_input_delay 0 [get_ports {qspi_1_dq}]
|
||||||
85
example/VCU118/fpga/fpga/Makefile
Normal file
85
example/VCU118/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,85 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu9p-flga2104-2L-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexuplus
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = ../rtl/fpga.sv
|
||||||
|
SYN_FILES += ../rtl/fpga_core.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/lss/taxi_mdio_master.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga.xdc
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||||
|
IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
program: $(PROJECT).bit
|
||||||
|
echo "open_hw" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||||
|
echo "open_hw" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
85
example/VCU118/fpga/fpga_10g/Makefile
Normal file
85
example/VCU118/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,85 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu9p-flga2104-2L-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexuplus
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = ../rtl/fpga.sv
|
||||||
|
SYN_FILES += ../rtl/fpga_core.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/lss/taxi_mdio_master.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||||
|
SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga.xdc
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||||
|
IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
program: $(PROJECT).bit
|
||||||
|
echo "open_hw" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||||
|
echo "open_hw" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
|
|
||||||
20
example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
20
example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,20 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0
|
||||||
|
|
||||||
|
set_property -dict [list \
|
||||||
|
CONFIG.Standard {SGMII} \
|
||||||
|
CONFIG.Physical_Interface {LVDS} \
|
||||||
|
CONFIG.Management_Interface {false} \
|
||||||
|
CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
|
||||||
|
CONFIG.LvdsRefClk {625} \
|
||||||
|
CONFIG.TxLane0_Placement {DIFF_PAIR_2} \
|
||||||
|
CONFIG.RxLane0_Placement {DIFF_PAIR_0} \
|
||||||
|
CONFIG.Tx_In_Upper_Nibble {0} \
|
||||||
|
] [get_ips sgmii_pcs_pma_0]
|
||||||
1
example/VCU118/fpga/lib/taxi
Symbolic link
1
example/VCU118/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../../../
|
||||||
529
example/VCU118/fpga/rtl/fpga.sv
Normal file
529
example/VCU118/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,529 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA top-level module
|
||||||
|
*/
|
||||||
|
module fpga #
|
||||||
|
(
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
parameter string FAMILY = "virtexuplus"
|
||||||
|
)
|
||||||
|
(
|
||||||
|
/*
|
||||||
|
* Clock: 125MHz LVDS
|
||||||
|
* Reset: Push button, active low
|
||||||
|
*/
|
||||||
|
input wire logic clk_125mhz_p,
|
||||||
|
input wire logic clk_125mhz_n,
|
||||||
|
input wire logic reset,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
input wire logic btnu,
|
||||||
|
input wire logic btnl,
|
||||||
|
input wire logic btnd,
|
||||||
|
input wire logic btnr,
|
||||||
|
input wire logic btnc,
|
||||||
|
input wire logic [3:0] sw,
|
||||||
|
output wire logic [7:0] led,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C for board management
|
||||||
|
*/
|
||||||
|
inout wire logic i2c_scl,
|
||||||
|
inout wire logic i2c_sda,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART: 115200 bps, 8N1
|
||||||
|
*/
|
||||||
|
input wire logic uart_rxd,
|
||||||
|
output wire logic uart_txd,
|
||||||
|
output wire logic uart_rts,
|
||||||
|
input wire logic uart_cts,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: 1000BASE-T SGMII
|
||||||
|
*/
|
||||||
|
input wire logic phy_sgmii_rx_p,
|
||||||
|
input wire logic phy_sgmii_rx_n,
|
||||||
|
output wire logic phy_sgmii_tx_p,
|
||||||
|
output wire logic phy_sgmii_tx_n,
|
||||||
|
input wire logic phy_sgmii_clk_p,
|
||||||
|
input wire logic phy_sgmii_clk_n,
|
||||||
|
output wire logic phy_reset_n,
|
||||||
|
input wire logic phy_int_n,
|
||||||
|
inout wire logic phy_mdio,
|
||||||
|
output wire logic phy_mdc,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
output wire logic [3:0] qsfp1_tx_p,
|
||||||
|
output wire logic [3:0] qsfp1_tx_n,
|
||||||
|
input wire logic [3:0] qsfp1_rx_p,
|
||||||
|
input wire logic [3:0] qsfp1_rx_n,
|
||||||
|
input wire logic qsfp1_mgt_refclk_0_p,
|
||||||
|
input wire logic qsfp1_mgt_refclk_0_n,
|
||||||
|
// input wire logic qsfp1_mgt_refclk_1_p,
|
||||||
|
// input wire logic qsfp1_mgt_refclk_1_n,
|
||||||
|
// output wire logic qsfp1_recclk_p,
|
||||||
|
// output wire logic qsfp1_recclk_n,
|
||||||
|
output wire logic qsfp1_modsell,
|
||||||
|
output wire logic qsfp1_resetl,
|
||||||
|
input wire logic qsfp1_modprsl,
|
||||||
|
input wire logic qsfp1_intl,
|
||||||
|
output wire logic qsfp1_lpmode,
|
||||||
|
|
||||||
|
output wire logic [3:0] qsfp2_tx_p,
|
||||||
|
output wire logic [3:0] qsfp2_tx_n,
|
||||||
|
input wire logic [3:0] qsfp2_rx_p,
|
||||||
|
input wire logic [3:0] qsfp2_rx_n,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_0_p,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_0_n,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_1_p,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_1_n,
|
||||||
|
// output wire logic qsfp2_recclk_p,
|
||||||
|
// output wire logic qsfp2_recclk_n,
|
||||||
|
output wire logic qsfp2_modsell,
|
||||||
|
output wire logic qsfp2_resetl,
|
||||||
|
input wire logic qsfp2_modprsl,
|
||||||
|
input wire logic qsfp2_intl,
|
||||||
|
output wire logic qsfp2_lpmode
|
||||||
|
);
|
||||||
|
|
||||||
|
// Clock and reset
|
||||||
|
|
||||||
|
wire clk_125mhz_ibufg;
|
||||||
|
|
||||||
|
// Internal 125 MHz clock
|
||||||
|
wire clk_125mhz_mmcm_out;
|
||||||
|
wire clk_125mhz_int;
|
||||||
|
wire rst_125mhz_int;
|
||||||
|
|
||||||
|
wire mmcm_rst = reset;
|
||||||
|
wire mmcm_locked;
|
||||||
|
wire mmcm_clkfb;
|
||||||
|
|
||||||
|
IBUFGDS #(
|
||||||
|
.DIFF_TERM("FALSE"),
|
||||||
|
.IBUF_LOW_PWR("FALSE")
|
||||||
|
)
|
||||||
|
clk_125mhz_ibufg_inst (
|
||||||
|
.O (clk_125mhz_ibufg),
|
||||||
|
.I (clk_125mhz_p),
|
||||||
|
.IB (clk_125mhz_n)
|
||||||
|
);
|
||||||
|
|
||||||
|
// MMCM instance
|
||||||
|
MMCME4_BASE #(
|
||||||
|
// 125 MHz input
|
||||||
|
.CLKIN1_PERIOD(8.0),
|
||||||
|
.REF_JITTER1(0.010),
|
||||||
|
// 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz)
|
||||||
|
.DIVCLK_DIVIDE(1),
|
||||||
|
// 125 MHz PFD * 10 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||||
|
.CLKFBOUT_MULT_F(10),
|
||||||
|
.CLKFBOUT_PHASE(0),
|
||||||
|
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||||
|
.CLKOUT0_DIVIDE_F(10),
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT0_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT1_DIVIDE(1),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT1_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT2_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT3_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT4_PHASE(0),
|
||||||
|
.CLKOUT4_CASCADE("FALSE"),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT5_PHASE(0),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT6_DIVIDE(1),
|
||||||
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||||
|
.CLKOUT6_PHASE(0),
|
||||||
|
|
||||||
|
// optimized bandwidth
|
||||||
|
.BANDWIDTH("OPTIMIZED"),
|
||||||
|
// don't wait for lock during startup
|
||||||
|
.STARTUP_WAIT("FALSE")
|
||||||
|
)
|
||||||
|
clk_mmcm_inst (
|
||||||
|
// 125 MHz input
|
||||||
|
.CLKIN1(clk_125mhz_ibufg),
|
||||||
|
// direct clkfb feeback
|
||||||
|
.CLKFBIN(mmcm_clkfb),
|
||||||
|
.CLKFBOUT(mmcm_clkfb),
|
||||||
|
.CLKFBOUTB(),
|
||||||
|
// 125 MHz, 0 degrees
|
||||||
|
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||||
|
.CLKOUT0B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT1(),
|
||||||
|
.CLKOUT1B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT2(),
|
||||||
|
.CLKOUT2B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT3(),
|
||||||
|
.CLKOUT3B(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT4(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT5(),
|
||||||
|
// Not used
|
||||||
|
.CLKOUT6(),
|
||||||
|
// reset input
|
||||||
|
.RST(mmcm_rst),
|
||||||
|
// don't power down
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
// locked output
|
||||||
|
.LOCKED(mmcm_locked)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG
|
||||||
|
clk_125mhz_bufg_inst (
|
||||||
|
.I(clk_125mhz_mmcm_out),
|
||||||
|
.O(clk_125mhz_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_sync_reset #(
|
||||||
|
.N(4)
|
||||||
|
)
|
||||||
|
sync_reset_125mhz_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(~mmcm_locked),
|
||||||
|
.out(rst_125mhz_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
// GPIO
|
||||||
|
wire btnu_int;
|
||||||
|
wire btnl_int;
|
||||||
|
wire btnd_int;
|
||||||
|
wire btnr_int;
|
||||||
|
wire btnc_int;
|
||||||
|
wire [3:0] sw_int;
|
||||||
|
|
||||||
|
taxi_debounce_switch #(
|
||||||
|
.WIDTH(9),
|
||||||
|
.N(4),
|
||||||
|
.RATE(156000)
|
||||||
|
)
|
||||||
|
debounce_switch_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.rst(rst_125mhz_int),
|
||||||
|
.in({btnu,
|
||||||
|
btnl,
|
||||||
|
btnd,
|
||||||
|
btnr,
|
||||||
|
btnc,
|
||||||
|
sw}),
|
||||||
|
.out({btnu_int,
|
||||||
|
btnl_int,
|
||||||
|
btnd_int,
|
||||||
|
btnr_int,
|
||||||
|
btnc_int,
|
||||||
|
sw_int})
|
||||||
|
);
|
||||||
|
|
||||||
|
wire uart_rxd_int;
|
||||||
|
wire uart_cts_int;
|
||||||
|
|
||||||
|
taxi_sync_signal #(
|
||||||
|
.WIDTH(2),
|
||||||
|
.N(2)
|
||||||
|
)
|
||||||
|
sync_signal_inst (
|
||||||
|
.clk(clk_125mhz_int),
|
||||||
|
.in({uart_rxd, uart_cts}),
|
||||||
|
.out({uart_rxd_int, uart_cts_int})
|
||||||
|
);
|
||||||
|
|
||||||
|
// SI570 I2C
|
||||||
|
wire i2c_scl_i;
|
||||||
|
wire i2c_scl_o = 1'b1;
|
||||||
|
wire i2c_scl_t = 1'b1;
|
||||||
|
wire i2c_sda_i;
|
||||||
|
wire i2c_sda_o = 1'b1;
|
||||||
|
wire i2c_sda_t = 1'b1;
|
||||||
|
|
||||||
|
assign i2c_scl_i = i2c_scl;
|
||||||
|
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
|
||||||
|
assign i2c_sda_i = i2c_sda;
|
||||||
|
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
|
||||||
|
|
||||||
|
// SGMII interface to PHY
|
||||||
|
wire phy_gmii_clk_int;
|
||||||
|
wire phy_gmii_rst_int;
|
||||||
|
wire phy_gmii_clk_en_int;
|
||||||
|
wire [7:0] phy_gmii_txd_int;
|
||||||
|
wire phy_gmii_tx_en_int;
|
||||||
|
wire phy_gmii_tx_er_int;
|
||||||
|
wire [7:0] phy_gmii_rxd_int;
|
||||||
|
wire phy_gmii_rx_dv_int;
|
||||||
|
wire phy_gmii_rx_er_int;
|
||||||
|
|
||||||
|
wire [15:0] pcspma_status_vector;
|
||||||
|
|
||||||
|
wire pcspma_status_link_status = pcspma_status_vector[0];
|
||||||
|
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
|
||||||
|
wire pcspma_status_rudi_c = pcspma_status_vector[2];
|
||||||
|
wire pcspma_status_rudi_i = pcspma_status_vector[3];
|
||||||
|
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
|
||||||
|
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
|
||||||
|
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
|
||||||
|
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
|
||||||
|
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
|
||||||
|
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
|
||||||
|
wire pcspma_status_duplex = pcspma_status_vector[12];
|
||||||
|
wire pcspma_status_remote_fault = pcspma_status_vector[13];
|
||||||
|
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
|
||||||
|
|
||||||
|
wire [4:0] pcspma_config_vector;
|
||||||
|
|
||||||
|
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
|
||||||
|
assign pcspma_config_vector[3] = 1'b0; // isolate
|
||||||
|
assign pcspma_config_vector[2] = 1'b0; // power down
|
||||||
|
assign pcspma_config_vector[1] = 1'b0; // loopback enable
|
||||||
|
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
|
||||||
|
|
||||||
|
wire [15:0] pcspma_an_config_vector;
|
||||||
|
|
||||||
|
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
|
||||||
|
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
|
||||||
|
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
|
||||||
|
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
|
||||||
|
assign pcspma_an_config_vector[9] = 1'b0; // reserved
|
||||||
|
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
|
||||||
|
assign pcspma_an_config_vector[6] = 1'b0; // reserved
|
||||||
|
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
|
||||||
|
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
|
||||||
|
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
|
||||||
|
|
||||||
|
sgmii_pcs_pma_0
|
||||||
|
eth_pcspma (
|
||||||
|
// SGMII
|
||||||
|
.txp_0 (phy_sgmii_tx_p),
|
||||||
|
.txn_0 (phy_sgmii_tx_n),
|
||||||
|
.rxp_0 (phy_sgmii_rx_p),
|
||||||
|
.rxn_0 (phy_sgmii_rx_n),
|
||||||
|
|
||||||
|
// Ref clock from PHY
|
||||||
|
.refclk625_p (phy_sgmii_clk_p),
|
||||||
|
.refclk625_n (phy_sgmii_clk_n),
|
||||||
|
|
||||||
|
// async reset
|
||||||
|
.reset (rst_125mhz_int),
|
||||||
|
|
||||||
|
// clock and reset outputs
|
||||||
|
.clk125_out (phy_gmii_clk_int),
|
||||||
|
.clk312_out (),
|
||||||
|
.rst_125_out (phy_gmii_rst_int),
|
||||||
|
.tx_logic_reset (),
|
||||||
|
.rx_logic_reset (),
|
||||||
|
.tx_locked (),
|
||||||
|
.rx_locked (),
|
||||||
|
.tx_pll_clk_out (),
|
||||||
|
.rx_pll_clk_out (),
|
||||||
|
|
||||||
|
// MAC clocking
|
||||||
|
.sgmii_clk_r_0 (),
|
||||||
|
.sgmii_clk_f_0 (),
|
||||||
|
.sgmii_clk_en_0 (phy_gmii_clk_en_int),
|
||||||
|
|
||||||
|
// Speed control
|
||||||
|
.speed_is_10_100_0 (pcspma_status_speed != 2'b10),
|
||||||
|
.speed_is_100_0 (pcspma_status_speed == 2'b01),
|
||||||
|
|
||||||
|
// Internal GMII
|
||||||
|
.gmii_txd_0 (phy_gmii_txd_int),
|
||||||
|
.gmii_tx_en_0 (phy_gmii_tx_en_int),
|
||||||
|
.gmii_tx_er_0 (phy_gmii_tx_er_int),
|
||||||
|
.gmii_rxd_0 (phy_gmii_rxd_int),
|
||||||
|
.gmii_rx_dv_0 (phy_gmii_rx_dv_int),
|
||||||
|
.gmii_rx_er_0 (phy_gmii_rx_er_int),
|
||||||
|
.gmii_isolate_0 (),
|
||||||
|
|
||||||
|
// Configuration
|
||||||
|
.configuration_vector_0 (pcspma_config_vector),
|
||||||
|
|
||||||
|
.an_interrupt_0 (),
|
||||||
|
.an_adv_config_vector_0 (pcspma_an_config_vector),
|
||||||
|
.an_restart_config_0 (1'b0),
|
||||||
|
|
||||||
|
// Status
|
||||||
|
.status_vector_0 (pcspma_status_vector),
|
||||||
|
.signal_detect_0 (1'b1),
|
||||||
|
|
||||||
|
// Cascade
|
||||||
|
.tx_bsc_rst_out (),
|
||||||
|
.rx_bsc_rst_out (),
|
||||||
|
.tx_bs_rst_out (),
|
||||||
|
.rx_bs_rst_out (),
|
||||||
|
.tx_rst_dly_out (),
|
||||||
|
.rx_rst_dly_out (),
|
||||||
|
.tx_bsc_en_vtc_out (),
|
||||||
|
.rx_bsc_en_vtc_out (),
|
||||||
|
.tx_bs_en_vtc_out (),
|
||||||
|
.rx_bs_en_vtc_out (),
|
||||||
|
.riu_clk_out (),
|
||||||
|
.riu_addr_out (),
|
||||||
|
.riu_wr_data_out (),
|
||||||
|
.riu_wr_en_out (),
|
||||||
|
.riu_nibble_sel_out (),
|
||||||
|
.riu_rddata_1 (16'b0),
|
||||||
|
.riu_valid_1 (1'b0),
|
||||||
|
.riu_prsnt_1 (1'b0),
|
||||||
|
.riu_rddata_2 (16'b0),
|
||||||
|
.riu_valid_2 (1'b0),
|
||||||
|
.riu_prsnt_2 (1'b0),
|
||||||
|
.riu_rddata_3 (16'b0),
|
||||||
|
.riu_valid_3 (1'b0),
|
||||||
|
.riu_prsnt_3 (1'b0),
|
||||||
|
.rx_btval_1 (),
|
||||||
|
.rx_btval_2 (),
|
||||||
|
.rx_btval_3 (),
|
||||||
|
.tx_dly_rdy_1 (1'b1),
|
||||||
|
.rx_dly_rdy_1 (1'b1),
|
||||||
|
.rx_vtc_rdy_1 (1'b1),
|
||||||
|
.tx_vtc_rdy_1 (1'b1),
|
||||||
|
.tx_dly_rdy_2 (1'b1),
|
||||||
|
.rx_dly_rdy_2 (1'b1),
|
||||||
|
.rx_vtc_rdy_2 (1'b1),
|
||||||
|
.tx_vtc_rdy_2 (1'b1),
|
||||||
|
.tx_dly_rdy_3 (1'b1),
|
||||||
|
.rx_dly_rdy_3 (1'b1),
|
||||||
|
.rx_vtc_rdy_3 (1'b1),
|
||||||
|
.tx_vtc_rdy_3 (1'b1),
|
||||||
|
.tx_rdclk_out ()
|
||||||
|
);
|
||||||
|
|
||||||
|
wire phy_mdio_i;
|
||||||
|
wire phy_mdio_o;
|
||||||
|
wire phy_mdio_t;
|
||||||
|
|
||||||
|
assign phy_mdio_i = phy_mdio;
|
||||||
|
assign phy_mdio = phy_mdio_t ? 1'bz : phy_mdio_o;
|
||||||
|
|
||||||
|
wire [7:0] led_int;
|
||||||
|
|
||||||
|
// SGMII interface debug:
|
||||||
|
// SW12:1 (sw[3]) off for payload byte, on for status vector
|
||||||
|
// SW12:4 (sw[0]) off for LSB of status vector, on for MSB
|
||||||
|
assign led = sw[3] ? (sw[0] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
|
||||||
|
|
||||||
|
fpga_core #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY)
|
||||||
|
)
|
||||||
|
core_inst (
|
||||||
|
/*
|
||||||
|
* Clock: 125 MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
.clk_125mhz(clk_125mhz_int),
|
||||||
|
.rst_125mhz(rst_125mhz_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
.btnu(btnu_int),
|
||||||
|
.btnl(btnl_int),
|
||||||
|
.btnd(btnd_int),
|
||||||
|
.btnr(btnr_int),
|
||||||
|
.btnc(btnc_int),
|
||||||
|
.sw(sw_int),
|
||||||
|
.led(led_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART: 115200 bps, 8N1
|
||||||
|
*/
|
||||||
|
.uart_rxd(uart_rxd_int),
|
||||||
|
.uart_txd(uart_txd),
|
||||||
|
.uart_rts(uart_rts),
|
||||||
|
.uart_cts(uart_cts_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: 1000BASE-T SGMII
|
||||||
|
*/
|
||||||
|
.phy_gmii_clk(phy_gmii_clk_int),
|
||||||
|
.phy_gmii_rst(phy_gmii_rst_int),
|
||||||
|
.phy_gmii_clk_en(phy_gmii_clk_en_int),
|
||||||
|
.phy_gmii_rxd(phy_gmii_rxd_int),
|
||||||
|
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
||||||
|
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
||||||
|
.phy_gmii_txd(phy_gmii_txd_int),
|
||||||
|
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
||||||
|
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
||||||
|
.phy_reset_n(phy_reset_n),
|
||||||
|
.phy_int_n(phy_int_n),
|
||||||
|
.phy_mdio_i(phy_mdio_i),
|
||||||
|
.phy_mdio_o(phy_mdio_o),
|
||||||
|
.phy_mdio_t(phy_mdio_t),
|
||||||
|
.phy_mdc(phy_mdc),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
.qsfp1_tx_p(qsfp1_tx_p),
|
||||||
|
.qsfp1_tx_n(qsfp1_tx_n),
|
||||||
|
.qsfp1_rx_p(qsfp1_rx_p),
|
||||||
|
.qsfp1_rx_n(qsfp1_rx_n),
|
||||||
|
.qsfp1_mgt_refclk_0_p(qsfp1_mgt_refclk_0_p),
|
||||||
|
.qsfp1_mgt_refclk_0_n(qsfp1_mgt_refclk_0_n),
|
||||||
|
// .qsfp1_mgt_refclk_1_p(qsfp1_mgt_refclk_1_p),
|
||||||
|
// .qsfp1_mgt_refclk_1_n(qsfp1_mgt_refclk_1_n),
|
||||||
|
// .qsfp1_recclk_p(qsfp1_recclk_p),
|
||||||
|
// .qsfp1_recclk_n(qsfp1_recclk_n),
|
||||||
|
.qsfp1_modsell(qsfp1_modsell),
|
||||||
|
.qsfp1_resetl(qsfp1_resetl),
|
||||||
|
.qsfp1_modprsl(qsfp1_modprsl),
|
||||||
|
.qsfp1_intl(qsfp1_intl),
|
||||||
|
.qsfp1_lpmode(qsfp1_lpmode),
|
||||||
|
|
||||||
|
.qsfp2_tx_p(qsfp2_tx_p),
|
||||||
|
.qsfp2_tx_n(qsfp2_tx_n),
|
||||||
|
.qsfp2_rx_p(qsfp2_rx_p),
|
||||||
|
.qsfp2_rx_n(qsfp2_rx_n),
|
||||||
|
// .qsfp2_mgt_refclk_0_p(qsfp2_mgt_refclk_0_p),
|
||||||
|
// .qsfp2_mgt_refclk_0_n(qsfp2_mgt_refclk_0_n),
|
||||||
|
// .qsfp2_mgt_refclk_1_p(qsfp2_mgt_refclk_1_p),
|
||||||
|
// .qsfp2_mgt_refclk_1_n(qsfp2_mgt_refclk_1_n),
|
||||||
|
// .qsfp2_recclk_p(qsfp2_recclk_p),
|
||||||
|
// .qsfp2_recclk_n(qsfp2_recclk_n),
|
||||||
|
.qsfp2_modsell(qsfp2_modsell),
|
||||||
|
.qsfp2_resetl(qsfp2_resetl),
|
||||||
|
.qsfp2_modprsl(qsfp2_modprsl),
|
||||||
|
.qsfp2_intl(qsfp2_intl),
|
||||||
|
.qsfp2_lpmode(qsfp2_lpmode)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
687
example/VCU118/fpga/rtl/fpga_core.sv
Normal file
687
example/VCU118/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,687 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA core logic
|
||||||
|
*/
|
||||||
|
module fpga_core #
|
||||||
|
(
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
parameter string FAMILY = "virtexuplus"
|
||||||
|
)
|
||||||
|
(
|
||||||
|
/*
|
||||||
|
* Clock: 125MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
input wire logic clk_125mhz,
|
||||||
|
input wire logic rst_125mhz,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
input wire logic btnu,
|
||||||
|
input wire logic btnl,
|
||||||
|
input wire logic btnd,
|
||||||
|
input wire logic btnr,
|
||||||
|
input wire logic btnc,
|
||||||
|
input wire logic [3:0] sw,
|
||||||
|
output wire logic [7:0] led,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART: 115200 bps, 8N1
|
||||||
|
*/
|
||||||
|
input wire logic uart_rxd,
|
||||||
|
output wire logic uart_txd,
|
||||||
|
output wire logic uart_rts,
|
||||||
|
input wire logic uart_cts,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: 1000BASE-T SGMII
|
||||||
|
*/
|
||||||
|
input wire logic phy_gmii_clk,
|
||||||
|
input wire logic phy_gmii_rst,
|
||||||
|
input wire logic phy_gmii_clk_en,
|
||||||
|
input wire logic [7:0] phy_gmii_rxd,
|
||||||
|
input wire logic phy_gmii_rx_dv,
|
||||||
|
input wire logic phy_gmii_rx_er,
|
||||||
|
output wire logic [7:0] phy_gmii_txd,
|
||||||
|
output wire logic phy_gmii_tx_en,
|
||||||
|
output wire logic phy_gmii_tx_er,
|
||||||
|
output wire logic phy_reset_n,
|
||||||
|
input wire logic phy_int_n,
|
||||||
|
input wire logic phy_mdio_i,
|
||||||
|
output wire logic phy_mdio_o,
|
||||||
|
output wire logic phy_mdio_t,
|
||||||
|
output wire logic phy_mdc,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
input wire logic [3:0] qsfp1_rx_p,
|
||||||
|
input wire logic [3:0] qsfp1_rx_n,
|
||||||
|
output wire logic [3:0] qsfp1_tx_p,
|
||||||
|
output wire logic [3:0] qsfp1_tx_n,
|
||||||
|
input wire logic qsfp1_mgt_refclk_0_p,
|
||||||
|
input wire logic qsfp1_mgt_refclk_0_n,
|
||||||
|
// input wire logic qsfp1_mgt_refclk_1_p,
|
||||||
|
// input wire logic qsfp1_mgt_refclk_1_n,
|
||||||
|
// output wire logic qsfp1_recclk_p,
|
||||||
|
// output wire logic qsfp1_recclk_n,
|
||||||
|
output wire logic qsfp1_modsell,
|
||||||
|
output wire logic qsfp1_resetl,
|
||||||
|
input wire logic qsfp1_modprsl,
|
||||||
|
input wire logic qsfp1_intl,
|
||||||
|
output wire logic qsfp1_lpmode,
|
||||||
|
|
||||||
|
input wire logic [3:0] qsfp2_rx_p,
|
||||||
|
input wire logic [3:0] qsfp2_rx_n,
|
||||||
|
output wire logic [3:0] qsfp2_tx_p,
|
||||||
|
output wire logic [3:0] qsfp2_tx_n,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_0_p,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_0_n,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_1_p,
|
||||||
|
// input wire logic qsfp2_mgt_refclk_1_n,
|
||||||
|
// output wire logic qsfp2_recclk_p,
|
||||||
|
// output wire logic qsfp2_recclk_n,
|
||||||
|
output wire logic qsfp2_modsell,
|
||||||
|
output wire logic qsfp2_resetl,
|
||||||
|
input wire logic qsfp2_modprsl,
|
||||||
|
input wire logic qsfp2_intl,
|
||||||
|
output wire logic qsfp2_lpmode
|
||||||
|
);
|
||||||
|
|
||||||
|
// assign led = 8'(sw);
|
||||||
|
|
||||||
|
// UART
|
||||||
|
assign uart_rts = 0;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(8)) axis_uart();
|
||||||
|
|
||||||
|
taxi_uart
|
||||||
|
uut (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream input (sink)
|
||||||
|
*/
|
||||||
|
.s_axis_tx(axis_uart),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream output (source)
|
||||||
|
*/
|
||||||
|
.m_axis_rx(axis_uart),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART interface
|
||||||
|
*/
|
||||||
|
.rxd(uart_rxd),
|
||||||
|
.txd(uart_txd),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.tx_busy(),
|
||||||
|
.rx_busy(),
|
||||||
|
.rx_overrun_error(),
|
||||||
|
.rx_frame_error(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.prescale(16'(125000000/115200/8))
|
||||||
|
);
|
||||||
|
|
||||||
|
// BASE-T PHY
|
||||||
|
assign phy_reset_n = !rst_125mhz;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
|
||||||
|
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||||
|
|
||||||
|
taxi_eth_mac_1g_fifo #(
|
||||||
|
.PADDING_EN(1),
|
||||||
|
.MIN_FRAME_LEN(64),
|
||||||
|
.TX_FIFO_DEPTH(16384),
|
||||||
|
.TX_FRAME_FIFO(1),
|
||||||
|
.RX_FIFO_DEPTH(16384),
|
||||||
|
.RX_FRAME_FIFO(1)
|
||||||
|
)
|
||||||
|
eth_mac_inst (
|
||||||
|
.rx_clk(phy_gmii_clk),
|
||||||
|
.rx_rst(phy_gmii_rst),
|
||||||
|
.tx_clk(phy_gmii_clk),
|
||||||
|
.tx_rst(phy_gmii_rst),
|
||||||
|
.logic_clk(clk_125mhz),
|
||||||
|
.logic_rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transmit interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.s_axis_tx(axis_eth),
|
||||||
|
.m_axis_tx_cpl(axis_tx_cpl),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.m_axis_rx(axis_eth),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GMII interface
|
||||||
|
*/
|
||||||
|
.gmii_rxd(phy_gmii_rxd),
|
||||||
|
.gmii_rx_dv(phy_gmii_rx_dv),
|
||||||
|
.gmii_rx_er(phy_gmii_rx_er),
|
||||||
|
.gmii_txd(phy_gmii_txd),
|
||||||
|
.gmii_tx_en(phy_gmii_tx_en),
|
||||||
|
.gmii_tx_er(phy_gmii_tx_er),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Control
|
||||||
|
*/
|
||||||
|
.rx_clk_enable(phy_gmii_clk_en),
|
||||||
|
.tx_clk_enable(phy_gmii_clk_en),
|
||||||
|
.rx_mii_select(1'b0),
|
||||||
|
.tx_mii_select(1'b0),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.tx_error_underflow(),
|
||||||
|
.tx_fifo_overflow(),
|
||||||
|
.tx_fifo_bad_frame(),
|
||||||
|
.tx_fifo_good_frame(),
|
||||||
|
.rx_error_bad_frame(),
|
||||||
|
.rx_error_bad_fcs(),
|
||||||
|
.rx_fifo_overflow(),
|
||||||
|
.rx_fifo_bad_frame(),
|
||||||
|
.rx_fifo_good_frame(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.cfg_ifg(8'd12),
|
||||||
|
.cfg_tx_enable(1'b1),
|
||||||
|
.cfg_rx_enable(1'b1)
|
||||||
|
);
|
||||||
|
|
||||||
|
// PHY MDIO init
|
||||||
|
reg [19:0] delay_reg = '1;
|
||||||
|
|
||||||
|
reg [1:0] mdio_cmd_st_reg = 2'b01; // clause 22
|
||||||
|
reg [1:0] mdio_cmd_op_reg = 2'b01; // write
|
||||||
|
reg [4:0] mdio_cmd_phy_addr_reg = 5'h03;
|
||||||
|
reg [4:0] mdio_cmd_reg_addr_reg = 5'h00;
|
||||||
|
reg [15:0] mdio_cmd_data_reg = '0;
|
||||||
|
reg mdio_cmd_valid_reg = 1'b0;
|
||||||
|
wire mdio_cmd_ready;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(32)) axis_mdio_cmd();
|
||||||
|
taxi_axis_if #(.DATA_W(16)) axis_mdio_rd_data();
|
||||||
|
|
||||||
|
assign axis_mdio_cmd.tdata = {mdio_cmd_st_reg, mdio_cmd_op_reg, mdio_cmd_phy_addr_reg, mdio_cmd_reg_addr_reg, 2'b10, mdio_cmd_data_reg};
|
||||||
|
assign axis_mdio_cmd.tvalid = mdio_cmd_valid_reg;
|
||||||
|
assign mdio_cmd_ready = axis_mdio_cmd.tready;
|
||||||
|
|
||||||
|
assign axis_mdio_rd_data.tready = 1'b1;
|
||||||
|
|
||||||
|
reg [3:0] state_reg = '0;
|
||||||
|
|
||||||
|
always_ff @(posedge clk_125mhz) begin
|
||||||
|
mdio_cmd_valid_reg <= mdio_cmd_valid_reg && !mdio_cmd_ready;
|
||||||
|
|
||||||
|
if (delay_reg != 0) begin
|
||||||
|
delay_reg <= delay_reg - 1;
|
||||||
|
end else if (mdio_cmd_valid_reg) begin
|
||||||
|
// wait for ready
|
||||||
|
state_reg <= state_reg;
|
||||||
|
end else begin
|
||||||
|
case (state_reg)
|
||||||
|
// set SGMII autonegotiation timer to 11 ms
|
||||||
|
// write 0x0070 to CFG4 (0x0031)
|
||||||
|
4'd0: begin
|
||||||
|
// write to REGCR to load address
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0D;
|
||||||
|
mdio_cmd_data_reg <= 16'h001F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd1;
|
||||||
|
end
|
||||||
|
4'd1: begin
|
||||||
|
// write address of CFG4 to ADDAR
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0E;
|
||||||
|
mdio_cmd_data_reg <= 16'h0031;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd2;
|
||||||
|
end
|
||||||
|
4'd2: begin
|
||||||
|
// write to REGCR to load data
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0D;
|
||||||
|
mdio_cmd_data_reg <= 16'h401F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd3;
|
||||||
|
end
|
||||||
|
4'd3: begin
|
||||||
|
// write data for CFG4 to ADDAR
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0E;
|
||||||
|
mdio_cmd_data_reg <= 16'h0070;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd4;
|
||||||
|
end
|
||||||
|
// enable SGMII clock output
|
||||||
|
// write 0x4000 to SGMIICTL1 (0x00D3)
|
||||||
|
4'd4: begin
|
||||||
|
// write to REGCR to load address
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0D;
|
||||||
|
mdio_cmd_data_reg <= 16'h001F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd5;
|
||||||
|
end
|
||||||
|
4'd5: begin
|
||||||
|
// write address of SGMIICTL1 to ADDAR
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0E;
|
||||||
|
mdio_cmd_data_reg <= 16'h00D3;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd6;
|
||||||
|
end
|
||||||
|
4'd6: begin
|
||||||
|
// write to REGCR to load data
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0D;
|
||||||
|
mdio_cmd_data_reg <= 16'h401F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd7;
|
||||||
|
end
|
||||||
|
4'd7: begin
|
||||||
|
// write data for SGMIICTL1 to ADDAR
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0E;
|
||||||
|
mdio_cmd_data_reg <= 16'h4000;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd8;
|
||||||
|
end
|
||||||
|
// enable 10Mbps operation
|
||||||
|
// write 0x0015 to 10M_SGMII_CFG (0x016F)
|
||||||
|
4'd8: begin
|
||||||
|
// write to REGCR to load address
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0D;
|
||||||
|
mdio_cmd_data_reg <= 16'h001F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd9;
|
||||||
|
end
|
||||||
|
4'd9: begin
|
||||||
|
// write address of 10M_SGMII_CFG to ADDAR
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0E;
|
||||||
|
mdio_cmd_data_reg <= 16'h016F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd10;
|
||||||
|
end
|
||||||
|
4'd10: begin
|
||||||
|
// write to REGCR to load data
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0D;
|
||||||
|
mdio_cmd_data_reg <= 16'h401F;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd11;
|
||||||
|
end
|
||||||
|
4'd11: begin
|
||||||
|
// write data for 10M_SGMII_CFG to ADDAR
|
||||||
|
mdio_cmd_reg_addr_reg <= 5'h0E;
|
||||||
|
mdio_cmd_data_reg <= 16'h0015;
|
||||||
|
mdio_cmd_valid_reg <= 1'b1;
|
||||||
|
state_reg <= 4'd12;
|
||||||
|
end
|
||||||
|
4'd12: begin
|
||||||
|
// done
|
||||||
|
state_reg <= 4'd12;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
// go to idle
|
||||||
|
state_reg <= 4'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
if (rst_125mhz) begin
|
||||||
|
state_reg <= '0;
|
||||||
|
delay_reg <= SIM ? 100 : '1;
|
||||||
|
mdio_cmd_valid_reg <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
taxi_mdio_master
|
||||||
|
mdio_master_inst (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
.s_axis_cmd(axis_mdio_cmd),
|
||||||
|
.m_axis_rd_data(axis_mdio_rd_data),
|
||||||
|
|
||||||
|
.mdc_o(phy_mdc),
|
||||||
|
.mdio_i(phy_mdio_i),
|
||||||
|
.mdio_o(phy_mdio_o),
|
||||||
|
.mdio_t(phy_mdio_t),
|
||||||
|
|
||||||
|
.busy(),
|
||||||
|
|
||||||
|
.prescale(8'd3)
|
||||||
|
);
|
||||||
|
|
||||||
|
// QSFP28
|
||||||
|
assign qsfp1_modsell = 1'b0;
|
||||||
|
assign qsfp1_resetl = 1'b1;
|
||||||
|
assign qsfp1_lpmode = 1'b0;
|
||||||
|
assign qsfp2_modsell = 1'b0;
|
||||||
|
assign qsfp2_resetl = 1'b1;
|
||||||
|
assign qsfp2_lpmode = 1'b0;
|
||||||
|
|
||||||
|
wire [7:0] qsfp_tx_clk;
|
||||||
|
wire [7:0] qsfp_tx_rst;
|
||||||
|
wire [7:0] qsfp_rx_clk;
|
||||||
|
wire [7:0] qsfp_rx_rst;
|
||||||
|
|
||||||
|
wire [7:0] qsfp_rx_status;
|
||||||
|
|
||||||
|
assign led = qsfp_rx_status;
|
||||||
|
|
||||||
|
wire [1:0] qsfp_gtpowergood;
|
||||||
|
|
||||||
|
wire qsfp1_mgt_refclk_0;
|
||||||
|
wire qsfp1_mgt_refclk_0_int;
|
||||||
|
wire qsfp1_mgt_refclk_0_bufg;
|
||||||
|
|
||||||
|
wire qsfp_rst;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[7:0]();
|
||||||
|
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[7:0]();
|
||||||
|
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
|
||||||
|
|
||||||
|
if (SIM) begin
|
||||||
|
|
||||||
|
assign qsfp1_mgt_refclk_0 = qsfp1_mgt_refclk_0_p;
|
||||||
|
assign qsfp1_mgt_refclk_0_int = qsfp1_mgt_refclk_0_p;
|
||||||
|
assign qsfp1_mgt_refclk_0_bufg = qsfp1_mgt_refclk_0_int;
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst (
|
||||||
|
.I (qsfp1_mgt_refclk_0_p),
|
||||||
|
.IB (qsfp1_mgt_refclk_0_n),
|
||||||
|
.CEB (1'b0),
|
||||||
|
.O (qsfp1_mgt_refclk_0),
|
||||||
|
.ODIV2 (qsfp1_mgt_refclk_0_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG_GT bufg_gt_qsfp1_mgt_refclk_0_inst (
|
||||||
|
.CE (&qsfp_gtpowergood),
|
||||||
|
.CEMASK (1'b1),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b1),
|
||||||
|
.DIV (3'd0),
|
||||||
|
.I (qsfp1_mgt_refclk_0_int),
|
||||||
|
.O (qsfp1_mgt_refclk_0_bufg)
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
taxi_sync_reset #(
|
||||||
|
.N(4)
|
||||||
|
)
|
||||||
|
qsfp_sync_reset_inst (
|
||||||
|
.clk(qsfp1_mgt_refclk_0_bufg),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
.out(qsfp_rst)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [7:0] qsfp_tx_p;
|
||||||
|
wire [7:0] qsfp_tx_n;
|
||||||
|
wire [7:0] qsfp_rx_p = {qsfp2_rx_p, qsfp1_rx_p};
|
||||||
|
wire [7:0] qsfp_rx_n = {qsfp2_rx_n, qsfp1_rx_n};
|
||||||
|
|
||||||
|
assign qsfp1_tx_p = qsfp_tx_p[3:0];
|
||||||
|
assign qsfp1_tx_n = qsfp_tx_n[3:0];
|
||||||
|
assign qsfp2_tx_p = qsfp_tx_p[7:4];
|
||||||
|
assign qsfp2_tx_n = qsfp_tx_n[7:4];
|
||||||
|
|
||||||
|
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
|
||||||
|
|
||||||
|
localparam CNT = 4;
|
||||||
|
|
||||||
|
taxi_eth_mac_25g_us #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
|
||||||
|
.CNT(4),
|
||||||
|
|
||||||
|
// GT type
|
||||||
|
.GT_TYPE("GTY"),
|
||||||
|
|
||||||
|
// PHY parameters
|
||||||
|
.PADDING_EN(1'b1),
|
||||||
|
.DIC_EN(1'b1),
|
||||||
|
.MIN_FRAME_LEN(64),
|
||||||
|
.PTP_TS_EN(1'b0),
|
||||||
|
.PTP_TS_FMT_TOD(1'b1),
|
||||||
|
.PTP_TS_W(96),
|
||||||
|
.PRBS31_EN(1'b0),
|
||||||
|
.TX_SERDES_PIPELINE(1),
|
||||||
|
.RX_SERDES_PIPELINE(1),
|
||||||
|
.COUNT_125US(125000/6.4)
|
||||||
|
)
|
||||||
|
mac_inst (
|
||||||
|
.xcvr_ctrl_clk(clk_125mhz),
|
||||||
|
.xcvr_ctrl_rst(qsfp_rst),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Common
|
||||||
|
*/
|
||||||
|
.xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
|
||||||
|
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0),
|
||||||
|
.xcvr_qpll0lock_out(),
|
||||||
|
.xcvr_qpll0clk_out(),
|
||||||
|
.xcvr_qpll0refclk_out(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial data
|
||||||
|
*/
|
||||||
|
.xcvr_txp(qsfp_tx_p[n*CNT +: CNT]),
|
||||||
|
.xcvr_txn(qsfp_tx_n[n*CNT +: CNT]),
|
||||||
|
.xcvr_rxp(qsfp_rx_p[n*CNT +: CNT]),
|
||||||
|
.xcvr_rxn(qsfp_rx_n[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MAC clocks
|
||||||
|
*/
|
||||||
|
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
|
||||||
|
.rx_rst_in('0),
|
||||||
|
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
|
||||||
|
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
|
||||||
|
.tx_rst_in('0),
|
||||||
|
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
|
||||||
|
.ptp_sample_clk('0),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transmit interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.s_axis_tx(axis_qsfp_tx[n*CNT +: CNT]),
|
||||||
|
.m_axis_tx_cpl(axis_qsfp_tx_cpl[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PTP clock
|
||||||
|
*/
|
||||||
|
.tx_ptp_ts('0),
|
||||||
|
.tx_ptp_ts_step('0),
|
||||||
|
.rx_ptp_ts('0),
|
||||||
|
.rx_ptp_ts_step('0),
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||||
|
*/
|
||||||
|
.tx_lfc_req('0),
|
||||||
|
.tx_lfc_resend('0),
|
||||||
|
.rx_lfc_en('0),
|
||||||
|
.rx_lfc_req(),
|
||||||
|
.rx_lfc_ack('0),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||||
|
*/
|
||||||
|
.tx_pfc_req('0),
|
||||||
|
.tx_pfc_resend('0),
|
||||||
|
.rx_pfc_en('0),
|
||||||
|
.rx_pfc_req(),
|
||||||
|
.rx_pfc_ack('0),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pause interface
|
||||||
|
*/
|
||||||
|
.tx_lfc_pause_en('0),
|
||||||
|
.tx_pause_req('0),
|
||||||
|
.tx_pause_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.tx_start_packet(),
|
||||||
|
.tx_error_underflow(),
|
||||||
|
.rx_start_packet(),
|
||||||
|
.rx_error_count(),
|
||||||
|
.rx_error_bad_frame(),
|
||||||
|
.rx_error_bad_fcs(),
|
||||||
|
.rx_bad_block(),
|
||||||
|
.rx_sequence_error(),
|
||||||
|
.rx_block_lock(),
|
||||||
|
.rx_high_ber(),
|
||||||
|
.rx_status(qsfp_rx_status[n*CNT +: CNT]),
|
||||||
|
.stat_tx_mcf(),
|
||||||
|
.stat_rx_mcf(),
|
||||||
|
.stat_tx_lfc_pkt(),
|
||||||
|
.stat_tx_lfc_xon(),
|
||||||
|
.stat_tx_lfc_xoff(),
|
||||||
|
.stat_tx_lfc_paused(),
|
||||||
|
.stat_tx_pfc_pkt(),
|
||||||
|
.stat_tx_pfc_xon(),
|
||||||
|
.stat_tx_pfc_xoff(),
|
||||||
|
.stat_tx_pfc_paused(),
|
||||||
|
.stat_rx_lfc_pkt(),
|
||||||
|
.stat_rx_lfc_xon(),
|
||||||
|
.stat_rx_lfc_xoff(),
|
||||||
|
.stat_rx_lfc_paused(),
|
||||||
|
.stat_rx_pfc_pkt(),
|
||||||
|
.stat_rx_pfc_xon(),
|
||||||
|
.stat_rx_pfc_xoff(),
|
||||||
|
.stat_rx_pfc_paused(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.cfg_ifg('{CNT{8'd12}}),
|
||||||
|
.cfg_tx_enable('1),
|
||||||
|
.cfg_rx_enable('1),
|
||||||
|
.cfg_tx_prbs31_enable('0),
|
||||||
|
.cfg_rx_prbs31_enable('0),
|
||||||
|
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||||
|
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||||
|
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||||
|
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||||
|
.cfg_mcf_rx_check_eth_src('0),
|
||||||
|
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||||
|
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||||
|
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||||
|
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||||
|
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||||
|
.cfg_mcf_rx_forward('0),
|
||||||
|
.cfg_mcf_rx_enable('0),
|
||||||
|
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||||
|
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||||
|
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||||
|
.cfg_tx_lfc_en('0),
|
||||||
|
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||||
|
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||||
|
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||||
|
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||||
|
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||||
|
.cfg_tx_pfc_en('0),
|
||||||
|
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||||
|
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||||
|
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||||
|
.cfg_rx_lfc_en('0),
|
||||||
|
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||||
|
.cfg_rx_pfc_en('0)
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
|
||||||
|
|
||||||
|
taxi_axis_async_fifo #(
|
||||||
|
.DEPTH(16384),
|
||||||
|
.RAM_PIPELINE(2),
|
||||||
|
.FRAME_FIFO(1),
|
||||||
|
.USER_BAD_FRAME_VALUE(1'b1),
|
||||||
|
.USER_BAD_FRAME_MASK(1'b1),
|
||||||
|
.DROP_OVERSIZE_FRAME(1),
|
||||||
|
.DROP_BAD_FRAME(1),
|
||||||
|
.DROP_WHEN_FULL(1)
|
||||||
|
)
|
||||||
|
ch_fifo (
|
||||||
|
/*
|
||||||
|
* AXI4-Stream input (sink)
|
||||||
|
*/
|
||||||
|
.s_clk(qsfp_rx_clk[n]),
|
||||||
|
.s_rst(qsfp_rx_rst[n]),
|
||||||
|
.s_axis(axis_qsfp_rx[n]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream output (source)
|
||||||
|
*/
|
||||||
|
.m_clk(qsfp_tx_clk[n]),
|
||||||
|
.m_rst(qsfp_tx_rst[n]),
|
||||||
|
.m_axis(axis_qsfp_tx[n]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pause
|
||||||
|
*/
|
||||||
|
.s_pause_req(1'b0),
|
||||||
|
.s_pause_ack(),
|
||||||
|
.m_pause_req(1'b0),
|
||||||
|
.m_pause_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.s_status_depth(),
|
||||||
|
.s_status_depth_commit(),
|
||||||
|
.s_status_overflow(),
|
||||||
|
.s_status_bad_frame(),
|
||||||
|
.s_status_good_frame(),
|
||||||
|
.m_status_depth(),
|
||||||
|
.m_status_depth_commit(),
|
||||||
|
.m_status_overflow(),
|
||||||
|
.m_status_bad_frame(),
|
||||||
|
.m_status_good_frame()
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
54
example/VCU118/fpga/tb/fpga_core/Makefile
Normal file
54
example/VCU118/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,54 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
|
||||||
|
TOPLEVEL_LANG = verilog
|
||||||
|
|
||||||
|
SIM ?= verilator
|
||||||
|
WAVES ?= 0
|
||||||
|
|
||||||
|
COCOTB_HDL_TIMEUNIT = 1ns
|
||||||
|
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||||
|
|
||||||
|
DUT = fpga_core
|
||||||
|
COCOTB_TEST_MODULES = test_$(DUT)
|
||||||
|
COCOTB_TOPLEVEL = $(DUT)
|
||||||
|
MODULE = $(COCOTB_TEST_MODULES)
|
||||||
|
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||||
|
VERILOG_SOURCES += ../../rtl/$(DUT).sv
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_mdio_master.sv
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||||
|
VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv
|
||||||
|
|
||||||
|
# handle file list files
|
||||||
|
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||||
|
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||||
|
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||||
|
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||||
|
|
||||||
|
# module parameters
|
||||||
|
export PARAM_SIM := "1'b1"
|
||||||
|
export PARAM_VENDOR := "\"XILINX\""
|
||||||
|
export PARAM_FAMILY := "\"virtexuplus\""
|
||||||
|
|
||||||
|
ifeq ($(SIM), icarus)
|
||||||
|
PLUSARGS += -fst
|
||||||
|
|
||||||
|
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||||
|
else ifeq ($(SIM), verilator)
|
||||||
|
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||||
|
|
||||||
|
ifeq ($(WAVES), 1)
|
||||||
|
COMPILE_ARGS += --trace-fst
|
||||||
|
VERILATOR_TRACE = 1
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||||
1
example/VCU118/fpga/tb/fpga_core/baser.py
Symbolic link
1
example/VCU118/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../lib/taxi/tb/eth/baser.py
|
||||||
286
example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
Normal file
286
example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,286 @@
|
|||||||
|
#!/usr/bin/env python
|
||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
"""
|
||||||
|
|
||||||
|
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
"""
|
||||||
|
|
||||||
|
import logging
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
|
||||||
|
import cocotb_test.simulator
|
||||||
|
|
||||||
|
import cocotb
|
||||||
|
from cocotb.log import SimLog
|
||||||
|
from cocotb.clock import Clock
|
||||||
|
from cocotb.triggers import RisingEdge, Combine
|
||||||
|
|
||||||
|
from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink
|
||||||
|
from cocotbext.eth import XgmiiFrame
|
||||||
|
from cocotbext.uart import UartSource, UartSink
|
||||||
|
|
||||||
|
try:
|
||||||
|
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||||
|
except ImportError:
|
||||||
|
# attempt import from current directory
|
||||||
|
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||||
|
try:
|
||||||
|
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||||
|
finally:
|
||||||
|
del sys.path[0]
|
||||||
|
|
||||||
|
|
||||||
|
class TB:
|
||||||
|
def __init__(self, dut, speed=1000e6):
|
||||||
|
self.dut = dut
|
||||||
|
|
||||||
|
self.log = SimLog("cocotb.tb")
|
||||||
|
self.log.setLevel(logging.DEBUG)
|
||||||
|
|
||||||
|
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||||
|
cocotb.start_soon(Clock(dut.phy_gmii_clk, 8, units="ns").start())
|
||||||
|
cocotb.start_soon(Clock(dut.qsfp1_mgt_refclk_0_p, 6.4, units="ns").start())
|
||||||
|
|
||||||
|
self.gmii_source = GmiiSource(dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv,
|
||||||
|
dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en)
|
||||||
|
self.gmii_sink = GmiiSink(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en,
|
||||||
|
dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en)
|
||||||
|
|
||||||
|
self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1)
|
||||||
|
self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1)
|
||||||
|
|
||||||
|
self.qsfp_sources = []
|
||||||
|
self.qsfp_sinks = []
|
||||||
|
|
||||||
|
for inst in dut.gty_quad:
|
||||||
|
for ch in inst.mac_inst.ch:
|
||||||
|
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
|
||||||
|
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
|
||||||
|
|
||||||
|
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
|
||||||
|
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
|
||||||
|
|
||||||
|
dut.phy_gmii_clk_en.setimmediatevalue(1)
|
||||||
|
|
||||||
|
dut.btnu.setimmediatevalue(0)
|
||||||
|
dut.btnl.setimmediatevalue(0)
|
||||||
|
dut.btnd.setimmediatevalue(0)
|
||||||
|
dut.btnr.setimmediatevalue(0)
|
||||||
|
dut.btnc.setimmediatevalue(0)
|
||||||
|
dut.sw.setimmediatevalue(0)
|
||||||
|
dut.uart_rts.setimmediatevalue(0)
|
||||||
|
|
||||||
|
async def init(self):
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||||
|
self.dut.phy_gmii_rst.setimmediatevalue(0)
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.value = 1
|
||||||
|
self.dut.phy_gmii_rst.value = 1
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.value = 0
|
||||||
|
self.dut.phy_gmii_rst.value = 0
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
|
||||||
|
async def uart_test(tb, source, sink):
|
||||||
|
tb.log.info("Test UART")
|
||||||
|
|
||||||
|
tx_data = b"FPGA"
|
||||||
|
|
||||||
|
tb.log.info("UART TX: %s", tx_data)
|
||||||
|
|
||||||
|
await source.write(tx_data)
|
||||||
|
|
||||||
|
rx_data = bytearray()
|
||||||
|
|
||||||
|
while len(rx_data) < len(tx_data):
|
||||||
|
rx_data.extend(await sink.read())
|
||||||
|
|
||||||
|
tb.log.info("UART RX: %s", rx_data)
|
||||||
|
|
||||||
|
tb.log.info("UART test done")
|
||||||
|
|
||||||
|
|
||||||
|
async def mac_test(tb, source, sink):
|
||||||
|
tb.log.info("Test MAC")
|
||||||
|
|
||||||
|
tb.log.info("Multiple small packets")
|
||||||
|
|
||||||
|
count = 64
|
||||||
|
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await source.send(GmiiFrame.from_payload(p))
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
rx_frame = await sink.recv()
|
||||||
|
|
||||||
|
tb.log.info("RX frame: %s", rx_frame)
|
||||||
|
|
||||||
|
assert rx_frame.get_payload() == pkts[k]
|
||||||
|
assert rx_frame.check_fcs()
|
||||||
|
assert rx_frame.error is None
|
||||||
|
|
||||||
|
tb.log.info("Multiple large packets")
|
||||||
|
|
||||||
|
count = 32
|
||||||
|
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await source.send(GmiiFrame.from_payload(p))
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
rx_frame = await sink.recv()
|
||||||
|
|
||||||
|
tb.log.info("RX frame: %s", rx_frame)
|
||||||
|
|
||||||
|
assert rx_frame.get_payload() == pkts[k]
|
||||||
|
assert rx_frame.check_fcs()
|
||||||
|
assert rx_frame.error is None
|
||||||
|
|
||||||
|
tb.log.info("MAC test done")
|
||||||
|
|
||||||
|
|
||||||
|
async def mac_test_25g(tb, source, sink):
|
||||||
|
tb.log.info("Test MAC")
|
||||||
|
|
||||||
|
tb.log.info("Multiple small packets")
|
||||||
|
|
||||||
|
count = 64
|
||||||
|
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await source.send(XgmiiFrame.from_payload(p))
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
rx_frame = await sink.recv()
|
||||||
|
|
||||||
|
tb.log.info("RX frame: %s", rx_frame)
|
||||||
|
|
||||||
|
assert rx_frame.get_payload() == pkts[k]
|
||||||
|
assert rx_frame.check_fcs()
|
||||||
|
|
||||||
|
tb.log.info("Multiple large packets")
|
||||||
|
|
||||||
|
count = 32
|
||||||
|
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await source.send(XgmiiFrame.from_payload(p))
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
rx_frame = await sink.recv()
|
||||||
|
|
||||||
|
tb.log.info("RX frame: %s", rx_frame)
|
||||||
|
|
||||||
|
assert rx_frame.get_payload() == pkts[k]
|
||||||
|
assert rx_frame.check_fcs()
|
||||||
|
|
||||||
|
tb.log.info("MAC test done")
|
||||||
|
|
||||||
|
|
||||||
|
@cocotb.test()
|
||||||
|
async def run_test(dut):
|
||||||
|
|
||||||
|
tb = TB(dut)
|
||||||
|
|
||||||
|
await tb.init()
|
||||||
|
|
||||||
|
tests = []
|
||||||
|
|
||||||
|
tb.log.info("Start UART test")
|
||||||
|
|
||||||
|
tests.append(cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink)))
|
||||||
|
|
||||||
|
tb.log.info("Start BASE-T MAC loopback test")
|
||||||
|
|
||||||
|
tests.append(cocotb.start_soon(mac_test(tb, tb.gmii_source, tb.gmii_sink)))
|
||||||
|
|
||||||
|
for k in range(len(tb.qsfp_sources)):
|
||||||
|
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||||
|
|
||||||
|
tests.append(cocotb.start_soon(mac_test_25g(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||||
|
|
||||||
|
await Combine(*tests)
|
||||||
|
|
||||||
|
await RisingEdge(dut.clk_125mhz)
|
||||||
|
await RisingEdge(dut.clk_125mhz)
|
||||||
|
|
||||||
|
|
||||||
|
# cocotb-test
|
||||||
|
|
||||||
|
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||||
|
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||||
|
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||||
|
|
||||||
|
|
||||||
|
def process_f_files(files):
|
||||||
|
lst = {}
|
||||||
|
for f in files:
|
||||||
|
if f[-2:].lower() == '.f':
|
||||||
|
with open(f, 'r') as fp:
|
||||||
|
l = fp.read().split()
|
||||||
|
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||||
|
lst[os.path.basename(f)] = f
|
||||||
|
else:
|
||||||
|
lst[os.path.basename(f)] = f
|
||||||
|
return list(lst.values())
|
||||||
|
|
||||||
|
|
||||||
|
def test_fpga_core(request):
|
||||||
|
dut = "fpga_core"
|
||||||
|
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||||
|
toplevel = dut
|
||||||
|
|
||||||
|
verilog_sources = [
|
||||||
|
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_mdio_master.sv"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
|
||||||
|
os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"),
|
||||||
|
]
|
||||||
|
|
||||||
|
verilog_sources = process_f_files(verilog_sources)
|
||||||
|
|
||||||
|
parameters = {}
|
||||||
|
|
||||||
|
parameters['SIM'] = "1'b1"
|
||||||
|
parameters['VENDOR'] = "\"XILINX\""
|
||||||
|
parameters['FAMILY'] = "\"virtexuplus\""
|
||||||
|
|
||||||
|
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||||
|
|
||||||
|
sim_build = os.path.join(tests_dir, "sim_build",
|
||||||
|
request.node.name.replace('[', '-').replace(']', ''))
|
||||||
|
|
||||||
|
cocotb_test.simulator.run(
|
||||||
|
simulator="verilator",
|
||||||
|
python_search=[tests_dir],
|
||||||
|
verilog_sources=verilog_sources,
|
||||||
|
toplevel=toplevel,
|
||||||
|
module=module,
|
||||||
|
parameters=parameters,
|
||||||
|
sim_build=sim_build,
|
||||||
|
extra_env=extra_env,
|
||||||
|
)
|
||||||
Reference in New Issue
Block a user