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eth: Add 1000BASE-X PCS core to AC701 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -4,18 +4,21 @@
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This example design targets the Xilinx AC701 FPGA board.
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The design places a looped-back MACs the BASE-T port, as well as XFCP on the USB UART for monitoring and control.
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The design places looped-back MACs on both the BASE-T port and the SFP+ cage, as well as XFCP on the USB UART for monitoring and control.
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* USB UART
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* XFCP (921600 baud)
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* RJ-45 Ethernet port with Marvell 88E1116 PHY
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* Looped-back MAC via RGMII
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* SFP+ cage
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* Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTX transceiver
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## Board details
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* FPGA: XC7A200T-2FBG676C
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* USB UART: Silicon Labs CP2103
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* 1000BASE-T PHY: Marvell 88E1116 via RGMII
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* 1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver
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## Licensing
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@@ -18,6 +18,7 @@ TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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# Files for synthesis
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SYN_FILES = $(RTL_DIR)/fpga.sv
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SYN_FILES += $(RTL_DIR)/fpga_core.sv
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SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
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SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
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SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
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@@ -32,6 +33,7 @@ XDC_FILES += ../syn/fpga.xdc
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XDC_FILES += ../syn/gpio.xdc
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XDC_FILES += ../syn/i2c.xdc
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XDC_FILES += ../syn/phy.xdc
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XDC_FILES += ../syn/sfp.xdc
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XDC_FILES += ../syn/eth_rgmii.xdc
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XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
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@@ -40,7 +42,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
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XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
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# IP
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#IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
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IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl
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# Configuration
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#CONFIG_TCL_FILES = ./config.tcl
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17
src/eth/example/AC701/fpga/ip/basex_pcs_pma_0.tcl
Normal file
17
src/eth/example/AC701/fpga/ip/basex_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,17 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0
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set_property -dict [list \
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CONFIG.Standard {1000BASEX} \
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CONFIG.Physical_Interface {Transceiver} \
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CONFIG.Management_Interface {false} \
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CONFIG.Auto_Negotiation {false} \
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CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
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] [get_ips basex_pcs_pma_0]
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@@ -1,7 +1,7 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2026 FPGA Ninja, LLC
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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@@ -61,6 +61,20 @@ module fpga #
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inout wire logic i2c_sda,
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output wire logic i2c_mux_reset,
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/*
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* Ethernet: SFP+
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*/
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input wire logic sfp_rx_p,
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input wire logic sfp_rx_n,
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output wire logic sfp_tx_p,
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output wire logic sfp_tx_n,
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input wire logic sfp_mgt_refclk_0_p,
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input wire logic sfp_mgt_refclk_0_n,
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output wire logic [1:0] sfp_mgt_clk_sel,
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output wire logic sfp_tx_disable,
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input wire logic sfp_rx_los,
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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@@ -259,6 +273,113 @@ assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
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// 1000BASE-X SFP
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assign sfp_mgt_clk_sel = 2'b00;
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wire sfp_gmii_clk_int;
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wire sfp_gmii_rst_int;
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wire sfp_gmii_clk_en_int;
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wire [7:0] sfp_gmii_txd_int;
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wire sfp_gmii_tx_en_int;
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wire sfp_gmii_tx_er_int;
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wire [7:0] sfp_gmii_rxd_int;
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wire sfp_gmii_rx_dv_int;
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wire sfp_gmii_rx_er_int;
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wire sfp_gtrefclk;
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wire sfp_gtrefclk_bufg;
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wire sfp_txuserclk;
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wire sfp_txuserclk2;
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wire sfp_rxuserclk;
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wire sfp_rxuserclk2;
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wire sfp_pma_reset;
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wire sfp_mmcm_locked;
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wire sfp_resetdone;
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assign sfp_gmii_clk_int = sfp_txuserclk2;
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_sfp_inst (
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.clk(sfp_gmii_clk_int),
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.rst(rst_int || !sfp_resetdone),
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.out(sfp_gmii_rst_int)
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);
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wire [15:0] sfp_status_vect;
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wire sfp_status_link_status = sfp_status_vect[0];
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wire sfp_status_link_synchronization = sfp_status_vect[1];
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wire sfp_status_rudi_c = sfp_status_vect[2];
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wire sfp_status_rudi_i = sfp_status_vect[3];
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wire sfp_status_rudi_invalid = sfp_status_vect[4];
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wire sfp_status_rxdisperr = sfp_status_vect[5];
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wire sfp_status_rxnotintable = sfp_status_vect[6];
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wire sfp_status_phy_link_status = sfp_status_vect[7];
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wire [1:0] sfp_status_remote_fault_encdg = sfp_status_vect[9:8];
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wire [1:0] sfp_status_speed = sfp_status_vect[11:10];
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wire sfp_status_duplex = sfp_status_vect[12];
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wire sfp_status_remote_fault = sfp_status_vect[13];
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wire [1:0] sfp_status_pause = sfp_status_vect[15:14];
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wire [4:0] sfp_config_vect;
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assign sfp_config_vect[4] = 1'b0; // autonegotiation enable
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assign sfp_config_vect[3] = 1'b0; // isolate
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assign sfp_config_vect[2] = 1'b0; // power down
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assign sfp_config_vect[1] = 1'b0; // loopback enable
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assign sfp_config_vect[0] = 1'b0; // unidirectional enable
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basex_pcs_pma_0
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sfp_pcspma (
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// Transceiver Interface
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.gtrefclk_p(sfp_mgt_refclk_0_p),
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.gtrefclk_n(sfp_mgt_refclk_0_n),
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.gtrefclk_out(sfp_gtrefclk),
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.gtrefclk_bufg_out(sfp_gtrefclk_bufg),
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.txp(sfp_tx_p),
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.txn(sfp_tx_n),
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.rxp(sfp_rx_p),
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.rxn(sfp_rx_n),
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.resetdone(sfp_resetdone),
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.userclk_out(sfp_txuserclk),
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.userclk2_out(sfp_txuserclk2),
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.rxuserclk_out(sfp_rxuserclk),
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.rxuserclk2_out(sfp_rxuserclk2),
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.independent_clock_bufg(clk_int),
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.pma_reset_out(sfp_pma_reset),
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.mmcm_locked_out(sfp_mmcm_locked),
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.gt0_pll0outclk_out(),
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.gt0_pll0outrefclk_out(),
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.gt0_pll1outclk_out(),
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.gt0_pll1outrefclk_out(),
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.gt0_pll0lock_out(),
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.gt0_pll0refclklost_out(),
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// GMII Interface
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.gmii_txd(sfp_gmii_txd_int),
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.gmii_tx_en(sfp_gmii_tx_en_int),
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.gmii_tx_er(sfp_gmii_tx_er_int),
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.gmii_rxd(sfp_gmii_rxd_int),
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.gmii_rx_dv(sfp_gmii_rx_dv_int),
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.gmii_rx_er(sfp_gmii_rx_er_int),
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.gmii_isolate(),
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// Management: Alternative to MDIO Interface
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.configuration_vector(sfp_config_vect),
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.status_vector(sfp_status_vect),
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// General IO's
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.reset(rst_int),
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.signal_detect(1'b1)
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);
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assign sfp_gmii_clk_en_int = 1'b1;
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// SGMII interface debug:
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// SW4:1 (sw[3]) off for payload byte, on for status vector
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// SW4:4 (sw[0]) off for LSB of status vector, on for MSB
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// assign led = sw[3] ? (sw[0] ? sfp_status_vect[15:8] : sfp_status_vect[7:0]) : led_int;
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wire [3:0] phy_rxd_int;
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wire phy_rx_ctl_int;
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@@ -334,7 +455,7 @@ core_inst (
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.btnr(btnr_int),
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.btnc(btnc_int),
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.sw(sw_int),
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.led(led_int),
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.led(led),
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/*
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* UART: 115200 bps, 8N1
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@@ -352,6 +473,21 @@ core_inst (
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.i2c_sda_i(i2c_sda_i),
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.i2c_sda_o(i2c_sda_o),
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/*
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* Ethernet: 1000BASE-X SFP
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*/
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.sfp_gmii_clk(sfp_gmii_clk_int),
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.sfp_gmii_rst(sfp_gmii_rst_int),
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.sfp_gmii_clk_en(sfp_gmii_clk_en_int),
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.sfp_gmii_rxd(sfp_gmii_rxd_int),
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.sfp_gmii_rx_dv(sfp_gmii_rx_dv_int),
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.sfp_gmii_rx_er(sfp_gmii_rx_er_int),
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.sfp_gmii_txd(sfp_gmii_txd_int),
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.sfp_gmii_tx_en(sfp_gmii_tx_en_int),
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.sfp_gmii_tx_er(sfp_gmii_tx_er_int),
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.sfp_tx_disable(sfp_tx_disable),
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.sfp_rx_los(sfp_rx_los),
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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@@ -22,7 +22,7 @@ module fpga_core #
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "kintex7",
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parameter string FAMILY = "artix7",
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// Use 90 degree clock for RGMII transmit
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parameter logic USE_CLK90 = 1'b1
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)
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@@ -62,6 +62,21 @@ module fpga_core #
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input wire logic i2c_sda_i,
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output wire logic i2c_sda_o,
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/*
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* Ethernet: 1000BASE-X SFP
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*/
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input wire logic sfp_gmii_clk,
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input wire logic sfp_gmii_rst,
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input wire logic sfp_gmii_clk_en,
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input wire logic [7:0] sfp_gmii_rxd,
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input wire logic sfp_gmii_rx_dv,
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input wire logic sfp_gmii_rx_er,
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output wire logic [7:0] sfp_gmii_txd,
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output wire logic sfp_gmii_tx_en,
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output wire logic sfp_gmii_tx_er,
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output wire logic sfp_tx_disable,
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input wire logic sfp_rx_los,
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/*
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* Ethernet: 1000BASE-T
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*/
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@@ -157,7 +172,7 @@ xfcp_stats_inst (
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.s_axis_stat(axis_stat)
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);
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taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[1]();
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taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[2]();
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taxi_axis_arb_mux #(
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.S_COUNT($size(axis_eth_stat)),
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@@ -229,7 +244,7 @@ taxi_eth_mac_1g_rgmii_fifo #(
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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baset_mac_inst (
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.gtx_clk(clk),
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.gtx_clk90(clk90),
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.gtx_rst(rst),
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@@ -288,6 +303,94 @@ eth_mac_inst (
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.cfg_rx_enable(1'b1)
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);
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// SFP+
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assign sfp_tx_disable = 1'b0;
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taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_eth();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.STAT_EN(1),
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.STAT_TX_LEVEL(1),
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.STAT_RX_LEVEL(1),
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.STAT_ID_BASE(16+16),
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.STAT_UPDATE_PERIOD(1024),
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.STAT_STR_EN(1),
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.STAT_PREFIX_STR("SFP"),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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sfp_mac_inst (
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.rx_clk(sfp_gmii_clk),
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.rx_rst(sfp_gmii_rst),
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.tx_clk(sfp_gmii_clk),
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.tx_rst(sfp_gmii_rst),
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.logic_clk(clk),
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.logic_rst(rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_sfp_eth),
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.m_axis_tx_cpl(axis_sfp_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_sfp_eth),
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/*
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* GMII interface
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*/
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.gmii_rxd(sfp_gmii_rxd),
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.gmii_rx_dv(sfp_gmii_rx_dv),
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.gmii_rx_er(sfp_gmii_rx_er),
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.gmii_txd(sfp_gmii_txd),
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.gmii_tx_en(sfp_gmii_tx_en),
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.gmii_tx_er(sfp_gmii_tx_er),
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/*
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* Control
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*/
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.rx_clk_enable(sfp_gmii_clk_en),
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.tx_clk_enable(sfp_gmii_clk_en),
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.rx_mii_select(1'b0),
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.tx_mii_select(1'b0),
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/*
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* Statistics
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*/
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.stat_clk(clk),
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.stat_rst(rst),
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.m_axis_stat(axis_eth_stat[1]),
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/*
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* Status
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*/
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.tx_error_underflow(),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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/*
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* Configuration
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*/
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.cfg_tx_max_pkt_len(16'd9218),
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.cfg_tx_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_max_pkt_len(16'd9218),
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.cfg_rx_enable(1'b1)
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);
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endmodule
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`resetall
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58
src/eth/example/AC701/fpga/syn/sfp.xdc
Normal file
58
src/eth/example/AC701/fpga/syn/sfp.xdc
Normal file
@@ -0,0 +1,58 @@
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# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx AC701 board
|
||||
# part: xc7a200tfbg676-2
|
||||
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||||
# GTX for Ethernet
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set_property -dict {LOC AC12} [get_ports sfp_rx_p] ;# MGTXRXP0_213 GTPE2_CHANNEL_X0Y0 / GTPE2_COMMON_X0Y0 from P3.13
|
||||
set_property -dict {LOC AD12} [get_ports sfp_rx_n] ;# MGTXRXN0_213 GTPE2_CHANNEL_X0Y0 / GTPE2_COMMON_X0Y0 from P3.12
|
||||
set_property -dict {LOC AC10} [get_ports sfp_tx_p] ;# MGTXTXP0_213 GTPE2_CHANNEL_X0Y0 / GTPE2_COMMON_X0Y0 from P3.18
|
||||
set_property -dict {LOC AD10} [get_ports sfp_tx_n] ;# MGTXTXN0_213 GTPE2_CHANNEL_X0Y0 / GTPE2_COMMON_X0Y0 from P3.19
|
||||
set_property -dict {LOC AA13} [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_213 from U3.10
|
||||
set_property -dict {LOC AB13} [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_213 from U3.11
|
||||
#set_property -dict {LOC AA11} [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_213 from U4.10
|
||||
#set_property -dict {LOC AB11} [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_213 from U4.11
|
||||
#set_property -dict {LOC D23 IOSTANDARD LVDS_25} [get_ports sfp_recclk_p] ;# to Si5324 U24.16 CKIN1_P
|
||||
#set_property -dict {LOC D24 IOSTANDARD LVDS_25} [get_ports sfp_recclk_n] ;# to Si5324 U24.17 CKIN1_N
|
||||
|
||||
#set_property -dict {LOC B24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
|
||||
#set_property -dict {LOC M19 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
|
||||
|
||||
set_property -dict {LOC R18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable}]
|
||||
set_property -dict {LOC R23 IOSTANDARD LVCMOS33} [get_ports {sfp_rx_los}]
|
||||
|
||||
# U3 clock mux for SFP_MGT_CLK_0
|
||||
# 2'b00 = EPHYCLK_Q0 (125 MHz)
|
||||
# 2'b01 = SI5324_OUT0
|
||||
# 2'b10 = FMC1_HPC_GBTCLK0
|
||||
# 2'b00 = NC
|
||||
set_property -dict {LOC B26 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports "sfp_mgt_clk_sel[0]"]
|
||||
set_property -dict {LOC C24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports "sfp_mgt_clk_sel[1]"]
|
||||
|
||||
# 125 MHz MGT reference clock (SGMII, 1000BASE-X)
|
||||
create_clock -period 8.000 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]
|
||||
|
||||
# U4 clock mux for SFP_MGT_CLK_1
|
||||
# 2'b00 = SMA_MGT_REFCLK
|
||||
# 2'b01 = SI5324_OUT1
|
||||
# 2'b10 = FMC1_HPC_GBTCLK1
|
||||
# 2'b00 = NC
|
||||
#set_property -dict {LOC A24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports "pcie_mgt_clk_sel[0]"]
|
||||
#set_property -dict {LOC C26 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports "pcie_mgt_clk_sel[1]"]
|
||||
|
||||
# 125 MHz MGT reference clock (SGMII, 1000BASE-X)
|
||||
#create_clock -period 6.400 -name sgmii_mgt_refclk_1 [get_ports sfp_mgt_refclk_1_p]
|
||||
|
||||
#set_false_path -to [get_ports {si5324_rst}]
|
||||
#set_output_delay 0 [get_ports {si5324_rst}]
|
||||
#set_false_path -from [get_ports {si5324_int}]
|
||||
#set_input_delay 0 [get_ports {si5324_int}]
|
||||
|
||||
set_false_path -to [get_ports {sfp_tx_disable}]
|
||||
set_output_delay 0 [get_ports {sfp_tx_disable}]
|
||||
@@ -23,6 +23,7 @@ COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
|
||||
@@ -12,7 +12,6 @@ Authors:
|
||||
import logging
|
||||
import os
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
@@ -30,14 +29,21 @@ class TB:
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# cocotb.start_soon(Clock(dut.phy_sgmii_clk, 8, units="ns").start())
|
||||
|
||||
self.baset_phy = RgmiiPhy(dut.phy_txd, dut.phy_tx_ctl, dut.phy_tx_clk,
|
||||
dut.phy_rxd, dut.phy_rx_ctl, dut.phy_rx_clk, speed=speed)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp_gmii_clk, 8, units="ns").start())
|
||||
|
||||
self.sfp_source = GmiiSource(dut.sfp_gmii_rxd, dut.sfp_gmii_rx_er, dut.sfp_gmii_rx_dv,
|
||||
dut.sfp_gmii_clk, dut.sfp_gmii_rst, dut.sfp_gmii_clk_en)
|
||||
self.sfp_sink = GmiiSink(dut.sfp_gmii_txd, dut.sfp_gmii_tx_er, dut.sfp_gmii_tx_en,
|
||||
dut.sfp_gmii_clk, dut.sfp_gmii_rst, dut.sfp_gmii_clk_en)
|
||||
|
||||
self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
|
||||
self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
|
||||
|
||||
dut.sfp_gmii_clk_en.setimmediatevalue(1)
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
dut.btnd.setimmediatevalue(0)
|
||||
@@ -51,16 +57,19 @@ class TB:
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
self.dut.sfp_gmii_rst.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 1
|
||||
self.dut.sfp_gmii_rst.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
self.dut.sfp_gmii_rst.value = 0
|
||||
|
||||
async def _run_clk(self):
|
||||
t = Timer(2, 'ns')
|
||||
@@ -130,6 +139,10 @@ async def run_test(dut):
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx)))
|
||||
|
||||
tb.log.info("Start SFP MAC loopback test")
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink)))
|
||||
|
||||
await Combine(*tests)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
@@ -164,6 +177,7 @@ def test_fpga_core(request):
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||
|
||||
Reference in New Issue
Block a user