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cndm: Add support to core logic for board control logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-17 14:32:15 -07:00
parent d9cf440351
commit cc888b2cca
12 changed files with 270 additions and 19 deletions
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30
src/cndm/tb/cndm.py
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@@ -26,6 +26,9 @@ CNDM_CMD_OP_CFG = 0x0100
CNDM_CMD_OP_ACCESS_REG = 0x0180
CNDM_CMD_OP_PTP = 0x0190
CNDM_CMD_OP_HWID = 0x01A0
CNDM_CMD_OP_HWMON = 0x01B0
CNDM_CMD_OP_PLL = 0x01C0
CNDM_CMD_OP_CREATE_EQ = 0x0200
CNDM_CMD_OP_MODIFY_EQ = 0x0201
@@ -63,6 +66,33 @@ CNDM_CMD_PTP_FLG_OFFSET_FNS = 0x00000010
CNDM_CMD_PTP_FLG_SET_PERIOD = 0x00000080
# Board operation commands
CNDM_CMD_BRD_OP_NOP = 0x0000
CNDM_CMD_BRD_OP_FLASH_RD = 0x0100
CNDM_CMD_BRD_OP_FLASH_WR = 0x0101
CNDM_CMD_BRD_OP_FLASH_CMD = 0x0108
CNDM_CMD_BRD_OP_EEPROM_RD = 0x0200
CNDM_CMD_BRD_OP_EEPROM_WR = 0x0201
CNDM_CMD_BRD_OP_OPTIC_RD = 0x0300
CNDM_CMD_BRD_OP_OPTIC_WR = 0x0301
CNDM_CMD_BRD_OP_HWID_SN_RD = 0x0400
CNDM_CMD_BRD_OP_HWID_VPD_RD = 0x0410
CNDM_CMD_BRD_OP_HWID_MAC_RD = 0x0480
CNDM_CMD_BRD_OP_PLL_STATUS_RD = 0x0500
CNDM_CMD_BRD_OP_PLL_TUNE_RAW_RD = 0x0502
CNDM_CMD_BRD_OP_PLL_TUNE_RAW_WR = 0x0503
CNDM_CMD_BRD_OP_PLL_TUNE_PPT_RD = 0x0504
CNDM_CMD_BRD_OP_PLL_TUNE_PPT_WR = 0x0505
CNDM_CMD_BRD_OP_I2C_RD = 0x8100
CNDM_CMD_BRD_OP_I2C_WR = 0x8101
class Eq:
def __init__(self, driver, port):
self.driver = driver

1
src/cndm/tb/cndm_lite_pcie_us/Makefile
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@@ -38,6 +38,7 @@ export PARAM_FAMILY := "\"virtexuplus\""
# Structural configuration
export PARAM_PORTS := 2
export PARAM_BRD_CTRL_EN := 0
export PARAM_SYS_CLK_PER_NS_NUM := 4
export PARAM_SYS_CLK_PER_NS_DEN := 1

7
src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.py
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@@ -20,7 +20,7 @@ import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.eth import EthMac
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
@@ -271,6 +271,10 @@ class TB:
self.dev.functions[0].configure_bar(0, 2**int(dut.uut.axil_ctrl_bar.ADDR_W))
# Board control
self.brd_ctrl_cmd = AxiStreamSink(AxiStreamBus(dut.m_axis_brd_ctrl_cmd), dut.pcie_clk, dut.pcie_rst)
self.brd_ctrl_rsp = AxiStreamSource(AxiStreamBus(dut.s_axis_brd_ctrl_rsp), dut.pcie_clk, dut.pcie_rst)
# PTP
cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
@@ -484,6 +488,7 @@ def test_cndm_lite_pcie_us(request, pcie_data_w, mac_data_w):
# Structural configuration
parameters['PORTS'] = 2
parameters['BRD_CTRL_EN'] = 0
parameters['SYS_CLK_PER_NS_NUM'] = 4
parameters['SYS_CLK_PER_NS_DEN'] = 1

17
src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.sv
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@@ -34,6 +34,7 @@ module test_cndm_lite_pcie_us #
// Structural configuration
parameter PORTS = 2,
parameter logic BRD_CTRL_EN = 1'b0,
parameter SYS_CLK_PER_NS_NUM = 4,
parameter SYS_CLK_PER_NS_DEN = 1,
@@ -155,6 +156,15 @@ logic [1:0] cfg_interrupt_msi_tph_type;
logic [7:0] cfg_interrupt_msi_tph_st_tag;
logic [7:0] cfg_interrupt_msi_function_number;
taxi_axis_if #(
.DATA_W(32),
.KEEP_EN(1),
.ID_EN(1),
.ID_W(4),
.USER_EN(1),
.USER_W(1)
) m_axis_brd_ctrl_cmd(), s_axis_brd_ctrl_rsp();
logic ptp_rst;
logic ptp_clk;
logic ptp_sample_clk;
@@ -328,6 +338,7 @@ cndm_lite_pcie_us #(
// Structural configuration
.PORTS(PORTS),
.BRD_CTRL_EN(BRD_CTRL_EN),
.SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM),
.SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN),
@@ -402,6 +413,12 @@ uut (
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* Board control
*/
.m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd),
.s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp),
/*
* PTP
*/

1
src/cndm/tb/cndm_micro_pcie_us/Makefile
View File

@@ -38,6 +38,7 @@ export PARAM_FAMILY := "\"virtexuplus\""
# Structural configuration
export PARAM_PORTS := 2
export PARAM_BRD_CTRL_EN := 0
export PARAM_SYS_CLK_PER_NS_NUM := 4
export PARAM_SYS_CLK_PER_NS_DEN := 1

7
src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py
View File

@@ -20,7 +20,7 @@ import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.eth import EthMac
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
@@ -271,6 +271,10 @@ class TB:
self.dev.functions[0].configure_bar(0, 2**int(dut.uut.axil_ctrl_bar.ADDR_W))
# Board control
self.brd_ctrl_cmd = AxiStreamSink(AxiStreamBus(dut.m_axis_brd_ctrl_cmd), dut.pcie_clk, dut.pcie_rst)
self.brd_ctrl_rsp = AxiStreamSource(AxiStreamBus(dut.s_axis_brd_ctrl_rsp), dut.pcie_clk, dut.pcie_rst)
# PTP
cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
@@ -483,6 +487,7 @@ def test_cndm_micro_pcie_us(request, pcie_data_w, mac_data_w):
# Structural configuration
parameters['PORTS'] = 2
parameters['BRD_CTRL_EN'] = 0
parameters['SYS_CLK_PER_NS_NUM'] = 4
parameters['SYS_CLK_PER_NS_DEN'] = 1

17
src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv
View File

@@ -34,6 +34,7 @@ module test_cndm_micro_pcie_us #
// Structural configuration
parameter PORTS = 2,
parameter logic BRD_CTRL_EN = 1'b0,
parameter SYS_CLK_PER_NS_NUM = 4,
parameter SYS_CLK_PER_NS_DEN = 1,
@@ -155,6 +156,15 @@ logic [1:0] cfg_interrupt_msi_tph_type;
logic [7:0] cfg_interrupt_msi_tph_st_tag;
logic [7:0] cfg_interrupt_msi_function_number;
taxi_axis_if #(
.DATA_W(32),
.KEEP_EN(1),
.ID_EN(1),
.ID_W(4),
.USER_EN(1),
.USER_W(1)
) m_axis_brd_ctrl_cmd(), s_axis_brd_ctrl_rsp();
logic ptp_rst;
logic ptp_clk;
logic ptp_sample_clk;
@@ -328,6 +338,7 @@ cndm_micro_pcie_us #(
// Structural configuration
.PORTS(PORTS),
.BRD_CTRL_EN(BRD_CTRL_EN),
.SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM),
.SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN),
@@ -402,6 +413,12 @@ uut (
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* Board control
*/
.m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd),
.s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp),
/*
* PTP
*/