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eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-14 22:54:09 -07:00
parent e993a6cfbf
commit cc8ec558bf
5 changed files with 18 additions and 19 deletions
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3
src/eth/rtl/taxi_eth_phy_10g_rx_ber_mon.sv
View File

@@ -18,7 +18,6 @@ Authors:
module taxi_eth_phy_10g_rx_ber_mon #
(
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter COUNT_125US = 125000/6.4
)
(
@@ -65,7 +64,7 @@ always_comb begin
rx_high_ber_next = rx_high_ber_reg;
if (GBX_IF_EN && !serdes_rx_hdr_valid) begin
if (!serdes_rx_hdr_valid) begin
// wait for header
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header

3
src/eth/rtl/taxi_eth_phy_10g_rx_frame_sync.sv
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@@ -18,7 +18,6 @@ Authors:
module taxi_eth_phy_10g_rx_frame_sync #
(
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 7
)
@@ -75,7 +74,7 @@ always_comb begin
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_COUNT_W'(BITSLIP_LOW_CYCLES);
end else if (GBX_IF_EN && !serdes_rx_hdr_valid) begin
end else if (!serdes_rx_hdr_valid) begin
// wait for header
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header

18
src/eth/rtl/taxi_eth_phy_10g_rx_if.sv
View File

@@ -66,9 +66,11 @@ module taxi_eth_phy_10g_rx_if #
input wire logic cfg_rx_prbs31_enable
);
localparam USE_HDR_VLD = GBX_IF_EN || DATA_W != 64;
// check configuration
if (DATA_W != 64)
$fatal(0, "Error: Interface width must be 64");
if (DATA_W != 32 && DATA_W != 64)
$fatal(0, "Error: Interface width must be 32 or 64");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
@@ -118,14 +120,14 @@ if (SERDES_PIPELINE > 0) begin
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_data_valid_int = serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_data_valid_int = GBX_IF_EN ? serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_valid_int = serdes_rx_hdr_valid_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_valid_int = USE_HDR_VLD ? serdes_rx_hdr_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_data_valid_int = serdes_rx_data_valid;
assign serdes_rx_data_valid_int = GBX_IF_EN ? serdes_rx_data_valid : 1'b1;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
assign serdes_rx_hdr_valid_int = serdes_rx_hdr_valid;
assign serdes_rx_hdr_valid_int = USE_HDR_VLD ? serdes_rx_hdr_valid : 1'b1;
end
wire [DATA_W-1:0] descrambled_rx_data;
@@ -226,7 +228,7 @@ end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_data_valid = GBX_IF_EN ? encoded_rx_data_valid_reg : 1'b1;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign encoded_rx_hdr_valid = GBX_IF_EN ? encoded_rx_hdr_valid_reg : 1'b1;
assign encoded_rx_hdr_valid = USE_HDR_VLD ? encoded_rx_hdr_valid_reg : 1'b1;
assign rx_error_count = rx_error_count_reg;
@@ -237,7 +239,6 @@ assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_EN && cfg_rx_pr
taxi_eth_phy_10g_rx_frame_sync #(
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
@@ -264,7 +265,6 @@ eth_phy_10g_rx_ber_mon_inst (
taxi_eth_phy_10g_rx_watchdog #(
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_watchdog_inst (

3
src/eth/rtl/taxi_eth_phy_10g_rx_watchdog.sv
View File

@@ -18,7 +18,6 @@ Authors:
module taxi_eth_phy_10g_rx_watchdog #
(
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter COUNT_125US = 125000/6.4
)
(
@@ -84,7 +83,7 @@ always_comb begin
rx_status_next = rx_status_reg;
if (rx_block_lock) begin
if (serdes_rx_hdr == SYNC_CTRL && (!GBX_IF_EN || serdes_rx_hdr_valid)) begin
if (serdes_rx_hdr == SYNC_CTRL && serdes_rx_hdr_valid) begin
saw_ctrl_sh_next = 1'b1;
end
if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin

10
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
View File

@@ -56,9 +56,11 @@ module taxi_eth_phy_10g_tx_if #
input wire logic cfg_tx_prbs31_enable
);
localparam USE_HDR_VLD = GBX_IF_EN || DATA_W != 64;
// check configuration
if (DATA_W != 64)
$fatal(0, "Error: Interface width must be 64");
if (DATA_W != 32 && DATA_W != 64)
$fatal(0, "Error: Interface width must be 32 or 64");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
@@ -129,13 +131,13 @@ if (SERDES_PIPELINE > 0) begin
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_hdr_valid = USE_HDR_VLD ? serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_gbx_sync = GBX_IF_EN ? serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1] : 1'b0;
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_reg : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_int;
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_reg : 1'b1;
assign serdes_tx_hdr_valid = USE_HDR_VLD ? serdes_tx_hdr_valid_reg : 1'b1;
assign serdes_tx_gbx_sync = GBX_IF_EN ? serdes_tx_gbx_sync_reg : 1'b0;
end