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https://github.com/fpganinja/taxi.git
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axis: Use signal sync module for async FIFO output pause
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -1,3 +1,4 @@
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taxi_axis_async_fifo.sv
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taxi_axis_async_fifo.sv
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../sync/taxi_sync_reset.sv
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../sync/taxi_sync_reset.sv
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../sync/taxi_sync_signal.sv
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taxi_axis_if.sv
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taxi_axis_if.sv
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@@ -802,24 +802,27 @@ if (PAUSE_EN) begin : pause
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logic pause_reg = 1'b0;
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logic pause_reg = 1'b0;
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logic pause_frame_reg = 1'b0;
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logic pause_frame_reg = 1'b0;
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logic s_pause_req_sync1_reg;
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wire s_pause_req_sync;
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logic s_pause_req_sync2_reg;
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logic s_pause_req_sync3_reg;
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logic s_pause_ack_sync1_reg;
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logic s_pause_ack_sync2_reg;
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logic s_pause_ack_sync3_reg;
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always_ff @(posedge s_clk) begin
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taxi_sync_signal #(
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s_pause_req_sync1_reg <= s_pause_req;
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.WIDTH(1),
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s_pause_ack_sync2_reg <= s_pause_ack_sync1_reg;
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.N(2)
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s_pause_ack_sync3_reg <= s_pause_ack_sync2_reg;
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)
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end
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pause_req_sync_inst (
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.clk(m_clk),
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.in(s_pause_req),
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.out(s_pause_req_sync)
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);
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always_ff @(posedge m_clk) begin
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taxi_sync_signal #(
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s_pause_req_sync2_reg <= s_pause_req_sync1_reg;
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.WIDTH(1),
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s_pause_req_sync3_reg <= s_pause_req_sync2_reg;
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.N(2)
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s_pause_ack_sync1_reg <= pause_reg;
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)
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end
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pause_ack_sync_inst (
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.clk(s_clk),
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.in(pause_reg),
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.out(s_pause_ack)
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);
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assign m_axis_tready_out = m_axis.tready && !pause_reg;
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assign m_axis_tready_out = m_axis.tready && !pause_reg;
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assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
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assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
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@@ -832,28 +835,27 @@ if (PAUSE_EN) begin : pause
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assign m_axis.tdest = m_axis_tdest_out;
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assign m_axis.tdest = m_axis_tdest_out;
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assign m_axis.tuser = m_axis_tuser_out;
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assign m_axis.tuser = m_axis_tuser_out;
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assign s_pause_ack = s_pause_ack_sync3_reg;
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assign m_pause_ack = pause_reg;
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assign m_pause_ack = pause_reg;
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always_ff @(posedge m_clk) begin
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always_ff @(posedge m_clk) begin
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if (FRAME_PAUSE) begin
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if (FRAME_PAUSE) begin
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if (pause_reg) begin
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if (pause_reg) begin
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// paused; update pause status
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// paused; update pause status
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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pause_reg <= m_pause_req || s_pause_req_sync;
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end else if (m_axis_tvalid_out) begin
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end else if (m_axis_tvalid_out) begin
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// frame transfer; set frame bit
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// frame transfer; set frame bit
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pause_frame_reg <= 1'b1;
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pause_frame_reg <= 1'b1;
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if (m_axis.tready && m_axis.tlast) begin
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if (m_axis.tready && m_axis.tlast) begin
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// end of frame; clear frame bit and update pause status
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// end of frame; clear frame bit and update pause status
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pause_frame_reg <= 1'b0;
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pause_frame_reg <= 1'b0;
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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pause_reg <= m_pause_req || s_pause_req_sync;
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end
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end
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end else if (!pause_frame_reg) begin
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end else if (!pause_frame_reg) begin
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// idle; update pause status
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// idle; update pause status
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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pause_reg <= m_pause_req || s_pause_req_sync;
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end
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end
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end else begin
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end else begin
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pause_reg <= m_pause_req || s_pause_req_sync3_reg;
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pause_reg <= m_pause_req || s_pause_req_sync;
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end
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end
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if (m_rst) begin
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if (m_rst) begin
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@@ -77,21 +77,4 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fi
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set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period
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set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period
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}
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}
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}
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}
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# pause sync
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set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_req_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_req_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_req_sync2_reg_reg"] -datapath_only $read_clk_period
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}
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set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_ack_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_ack_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_ack_sync2_reg_reg"] -datapath_only $write_clk_period
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}
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}
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}
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