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eth: Use correct clock for TX completions in MAC + FIFO testbenches

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-16 18:59:18 -08:00
parent 5c8037093b
commit d01a90298c
3 changed files with 3 additions and 3 deletions
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2
tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py
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@@ -46,7 +46,7 @@ class TB:
dut.tx_clk, dut.tx_rst, dut.tx_clk_enable, dut.tx_mii_select)
self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
dut.rx_clk_enable.setimmediatevalue(1)