xfcp: Use SV enums in XFCP

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/xfcp/rtl/taxi_xfcp_mod_apb.sv

@@ -143,19 +143,20 @@ initial begin
     end
 end
 
-localparam [3:0]
-    STATE_IDLE = 4'd0,
-    STATE_HEADER_1 = 4'd1,
-    STATE_HEADER_2 = 4'd2,
-    STATE_HEADER_3 = 4'd3,
-    STATE_READ_1 = 4'd4,
-    STATE_READ_2 = 4'd5,
-    STATE_WRITE_1 = 4'd6,
-    STATE_WRITE_2 = 4'd7,
-    STATE_WAIT_LAST = 4'd8,
-    STATE_ID = 4'd9;
+typedef enum logic [3:0] {
+    STATE_IDLE,
+    STATE_HEADER_1,
+    STATE_HEADER_2,
+    STATE_HEADER_3,
+    STATE_READ_1,
+    STATE_READ_2,
+    STATE_WRITE_1,
+    STATE_WRITE_2,
+    STATE_WAIT_LAST,
+    STATE_ID
+} state_t;
 
-logic [3:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic [COUNT_SIZE-1:0] ptr_reg = '0, ptr_next;
 logic [7:0] count_reg = 8'd0, count_next;

src/xfcp/rtl/taxi_xfcp_mod_axil.sv

@@ -144,19 +144,20 @@ initial begin
     end
 end
 
-localparam [3:0]
-    STATE_IDLE = 4'd0,
-    STATE_HEADER_1 = 4'd1,
-    STATE_HEADER_2 = 4'd2,
-    STATE_HEADER_3 = 4'd3,
-    STATE_READ_1 = 4'd4,
-    STATE_READ_2 = 4'd5,
-    STATE_WRITE_1 = 4'd6,
-    STATE_WRITE_2 = 4'd7,
-    STATE_WAIT_LAST = 4'd8,
-    STATE_ID = 4'd9;
+typedef enum logic [3:0] {
+    STATE_IDLE,
+    STATE_HEADER_1,
+    STATE_HEADER_2,
+    STATE_HEADER_3,
+    STATE_READ_1,
+    STATE_READ_2,
+    STATE_WRITE_1,
+    STATE_WRITE_2,
+    STATE_WAIT_LAST,
+    STATE_ID
+} state_t;
 
-logic [3:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic [COUNT_SIZE-1:0] ptr_reg = '0, ptr_next;
 logic [7:0] count_reg = 8'd0, count_next;
@@ -621,7 +622,7 @@ always_comb begin
     store_xfcp_usp_us_int_to_output = 1'b0;
     store_xfcp_usp_us_int_to_temp = 1'b0;
     store_xfcp_usp_us_temp_to_output = 1'b0;
-    
+
     if (xfcp_usp_us_tready_int_reg) begin
         // input is ready
         if (xfcp_usp_us.tready || !xfcp_usp_us_tvalid_reg) begin
@@ -667,7 +668,7 @@ always_ff @(posedge clk) begin
         xfcp_usp_us_tvalid_reg <= 1'b0;
         xfcp_usp_us_tready_int_reg <= 1'b0;
         temp_xfcp_usp_us_tvalid_reg <= 1'b0;
-    end 
+    end
 end
 
 endmodule

src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv

@@ -105,22 +105,23 @@ initial begin
     end
 end
 
-localparam [3:0]
-    STATE_IDLE = 4'd0,
-    STATE_HEADER_1 = 4'd1,
-    STATE_HEADER_2 = 4'd2,
-    STATE_PROCESS = 4'd3,
-    STATE_STATUS = 4'd4,
-    STATE_PRESCALE_L = 4'd5,
-    STATE_PRESCALE_H = 4'd6,
-    STATE_COUNT = 4'd7,
-    STATE_NEXT_CMD= 4'd8,
-    STATE_WRITE_DATA = 4'd9,
-    STATE_READ_DATA = 4'd10,
-    STATE_WAIT_LAST = 4'd11,
-    STATE_ID = 4'd12;
+typedef enum logic [3:0] {
+    STATE_IDLE,
+    STATE_HEADER_1,
+    STATE_HEADER_2,
+    STATE_PROCESS,
+    STATE_STATUS,
+    STATE_PRESCALE_L,
+    STATE_PRESCALE_H,
+    STATE_COUNT,
+    STATE_NEXT_CMD,
+    STATE_WRITE_DATA,
+    STATE_READ_DATA,
+    STATE_WAIT_LAST,
+    STATE_ID
+} state_t;
 
-logic [3:0] state_reg = STATE_IDLE, state_next;
+state_t state_reg = STATE_IDLE, state_next;
 
 logic [7:0] count_reg = 8'd0, count_next;
 
@@ -201,9 +202,9 @@ always_comb begin
     i2c_wr_data_next = i2c_wr_data_reg;
     i2c_wr_data_valid_next = i2c_wr_data_valid_reg && !i2c_wr_data.tready;
     i2c_wr_data_last_next = i2c_wr_data_last_reg;
-    
+
     i2c_rd_data_ready_next = 1'b0;
-    
+
     prescale_next = prescale_reg;
     stop_on_idle_next = stop_on_idle_reg;
 
@@ -726,7 +727,7 @@ always_comb begin
     store_up_xfcp_int_to_output = 1'b0;
     store_up_xfcp_int_to_temp = 1'b0;
     store_up_xfcp_temp_to_output = 1'b0;
-    
+
     if (xfcp_usp_us_tready_int_reg) begin
         // input is ready
         if (xfcp_usp_us.tready || !xfcp_usp_us_tvalid_reg) begin

src/xfcp/rtl/taxi_xfcp_switch.sv

@@ -108,20 +108,22 @@ initial begin
     end
 end
 
-localparam [2:0]
-    DN_STATE_IDLE = 3'd0,
-    DN_STATE_TRANSFER = 3'd1,
-    DN_STATE_HEADER = 3'd2,
-    DN_STATE_PKT = 3'd3,
-    DN_STATE_ID = 3'd4;
+typedef enum logic [2:0] {
+    DN_STATE_IDLE,
+    DN_STATE_TRANSFER,
+    DN_STATE_HEADER,
+    DN_STATE_PKT,
+    DN_STATE_ID
+} dn_state_t;
 
-logic [2:0] dn_state_reg = DN_STATE_IDLE, dn_state_next;
+dn_state_t dn_state_reg = DN_STATE_IDLE, dn_state_next;
 
-localparam [0:0]
-    UP_STATE_IDLE = 1'd0,
-    UP_STATE_TRANSFER = 1'd1;
+typedef enum logic [0:0] {
+    UP_STATE_IDLE,
+    UP_STATE_TRANSFER
+} up_state_t;
 
-logic [0:0] up_state_reg = UP_STATE_IDLE, up_state_next;
+up_state_t up_state_reg = UP_STATE_IDLE, up_state_next;
 
 logic [CL_PORTS-1:0] dn_select_reg = '0, dn_select_next;
 logic dn_frame_reg = 1'b0, dn_frame_next;
@@ -143,14 +145,14 @@ logic       xfcp_usp_us_tvalid_int;
 logic       xfcp_usp_us_tready_int_reg = 1'b0;
 logic       xfcp_usp_us_tlast_int;
 logic       xfcp_usp_us_tuser_int;
-wire      xfcp_usp_us_tready_int_early;
+wire        xfcp_usp_us_tready_int_early;
 
 logic [7:0]       xfcp_dsp_ds_tdata_int;
 logic [PORTS-1:0] xfcp_dsp_ds_tvalid_int;
 logic             xfcp_dsp_ds_tready_int_reg = 1'b0;
 logic             xfcp_dsp_ds_tlast_int;
 logic             xfcp_dsp_ds_tuser_int;
-wire            xfcp_dsp_ds_tready_int_early;
+wire              xfcp_dsp_ds_tready_int_early;
 
 logic [7:0] int_loop_tdata_reg = 8'd0, int_loop_tdata_next;
 logic       int_loop_tvalid_reg = 1'b0, int_loop_tvalid_next;