example/KCU105: Add XFCP to KCU105 example design for monitoring and control

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/KCU105/fpga/README.md

@@ -4,10 +4,10 @@
 
 This example design targets the Xilinx KCU105 FPGA board.
 
-The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as a looped-back UART on on the USB UART connection.
+The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as XFCP on the USB UART for monitoring and control.
 
 *  USB UART
-    *  Looped-back UART
+    *  XFCP (921600 baud)
 *  RJ-45 Ethernet port with Marvell 88E1111 PHY
     *  Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
 *  SFP+ cages
@@ -37,6 +37,4 @@ Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensu
 
 Run `make program` to program the board with Vivado.
 
-To test the looped-back UART, use any serial terminal software like minicom, screen, etc.  The looped-back UART will echo typed text back without modification.
-
 To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.

example/KCU105/fpga/fpga_10g/Makefile

@@ -16,7 +16,9 @@ SYN_FILES = ../rtl/fpga.sv
 SYN_FILES += ../rtl/fpga_core.sv
 SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
 SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f
+SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
+SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
+SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
 SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
 SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
 SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv

example/KCU105/fpga/fpga_1g/Makefile

@@ -15,7 +15,9 @@ FPGA_ARCH = kintexu
 SYN_FILES = ../rtl/fpga.sv
 SYN_FILES += ../rtl/fpga_core.sv
 SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
-SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f
+SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
+SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
+SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
 SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
 SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
 SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv

example/KCU105/fpga/rtl/fpga_core.sv

@@ -103,44 +103,108 @@ module fpga_core #
 
 assign led = sw;
 
-// UART
+// XFCP
 assign uart_cts = 1'b0;
 
-taxi_axis_if #(.DATA_W(8)) axis_uart();
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
 
-taxi_uart
+taxi_xfcp_if_uart #(
-uart_inst (
+    .TX_FIFO_DEPTH(512),
+    .RX_FIFO_DEPTH(512)
+)
+xfcp_if_uart_inst (
     .clk(clk),
     .rst(rst),
 
-    /*
-     * AXI4-Stream input (sink)
-     */
-    .s_axis_tx(axis_uart),
-
-    /*
-     * AXI4-Stream output (source)
-     */
-    .m_axis_rx(axis_uart),
-
     /*
      * UART interface
      */
-    .rxd(uart_rxd),
+    .uart_rxd(uart_rxd),
-    .txd(uart_txd),
+    .uart_txd(uart_txd),
 
     /*
-     * Status
+     * XFCP downstream interface
      */
-    .tx_busy(),
+    .xfcp_dsp_ds(xfcp_ds),
-    .rx_busy(),
+    .xfcp_dsp_us(xfcp_us),
-    .rx_overrun_error(),
-    .rx_frame_error(),
 
     /*
      * Configuration
      */
-    .prescale(16'(125000000/115200))
+    .prescale(16'(125000000/921600))
+);
+
+taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
+
+taxi_xfcp_switch #(
+    .XFCP_ID_STR("KCU105"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR("Taxi example"),
+    .PORTS($size(xfcp_sw_us))
+)
+xfcp_sw_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_ds),
+    .xfcp_usp_us(xfcp_us),
+
+    /*
+     * XFCP downstream ports
+     */
+    .xfcp_dsp_ds(xfcp_sw_ds),
+    .xfcp_dsp_us(xfcp_sw_us)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
+
+taxi_xfcp_mod_stats #(
+    .XFCP_ID_STR("Statistics"),
+    .XFCP_EXT_ID(0),
+    .XFCP_EXT_ID_STR(""),
+    .STAT_COUNT_W(64),
+    .STAT_PIPELINE(2)
+)
+xfcp_stats_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .xfcp_usp_ds(xfcp_sw_ds[0]),
+    .xfcp_usp_us(xfcp_sw_us[0]),
+
+    /*
+     * Statistics increment input
+     */
+    .s_axis_stat(axis_stat)
+);
+
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[SFP_RATE ? 2 : 3]();
+
+taxi_axis_arb_mux #(
+    .S_COUNT($size(axis_eth_stat)),
+    .UPDATE_TID(1'b0),
+    .ARB_ROUND_ROBIN(1'b1),
+    .ARB_LSB_HIGH_PRIO(1'b0)
+)
+stat_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream inputs (sink)
+     */
+    .s_axis(axis_eth_stat),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(axis_stat)
 );
 
 // BASE-T PHY
@@ -148,12 +212,15 @@ assign phy_reset_n = !rst;
 
 taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
-taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_stat();
 
 taxi_eth_mac_1g_fifo #(
     .PADDING_EN(1),
     .MIN_FRAME_LEN(64),
-    .STAT_EN(1'b0),
+    .STAT_EN(1),
+    .STAT_TX_LEVEL(1),
+    .STAT_RX_LEVEL(1),
+    .STAT_ID_BASE(0),
+    .STAT_UPDATE_PERIOD(1024),
     .TX_FIFO_DEPTH(16384),
     .TX_FRAME_FIFO(1),
     .RX_FIFO_DEPTH(16384),
@@ -201,7 +268,7 @@ eth_mac_inst (
      */
     .stat_clk(clk),
     .stat_rst(rst),
-    .m_axis_stat(axis_stat),
+    .m_axis_stat(axis_eth_stat[0]),
 
     /*
      * Status
@@ -233,16 +300,18 @@ if (SFP_RATE == 0) begin : sfp_mac
 
     taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp0_eth();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp0_tx_cpl();
-    taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp0_stat();
 
     taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp1_eth();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp1_tx_cpl();
-    taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp1_stat();
 
     taxi_eth_mac_1g_fifo #(
         .PADDING_EN(1),
         .MIN_FRAME_LEN(64),
-        .STAT_EN(1'b0),
+        .STAT_EN(1),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE((16+16)+(16+16)*0),
+        .STAT_UPDATE_PERIOD(1024),
         .TX_FIFO_DEPTH(16384),
         .TX_FRAME_FIFO(1),
         .RX_FIFO_DEPTH(16384),
@@ -290,7 +359,7 @@ if (SFP_RATE == 0) begin : sfp_mac
          */
         .stat_clk(clk),
         .stat_rst(rst),
-        .m_axis_stat(axis_sfp0_stat),
+        .m_axis_stat(axis_eth_stat[1]),
 
         /*
          * Status
@@ -318,7 +387,11 @@ if (SFP_RATE == 0) begin : sfp_mac
     taxi_eth_mac_1g_fifo #(
         .PADDING_EN(1),
         .MIN_FRAME_LEN(64),
-        .STAT_EN(1'b0),
+        .STAT_EN(1),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE((16+16)+(16+16)*1),
+        .STAT_UPDATE_PERIOD(1024),
         .TX_FIFO_DEPTH(16384),
         .TX_FRAME_FIFO(1),
         .RX_FIFO_DEPTH(16384),
@@ -366,7 +439,7 @@ if (SFP_RATE == 0) begin : sfp_mac
          */
         .stat_clk(clk),
         .stat_rst(rst),
-        .m_axis_stat(axis_sfp1_stat),
+        .m_axis_stat(axis_eth_stat[2]),
 
         /*
          * Status
@@ -411,7 +484,6 @@ end else begin : sfp_mac
     taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[2]();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
     taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[2]();
-    taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat();
 
     if (SIM) begin
 
@@ -471,7 +543,11 @@ end else begin : sfp_mac
         .TX_SERDES_PIPELINE(1),
         .RX_SERDES_PIPELINE(1),
         .COUNT_125US(125000/6.4),
-        .STAT_EN(1'b0)
+        .STAT_EN(1),
+        .STAT_TX_LEVEL(1),
+        .STAT_RX_LEVEL(1),
+        .STAT_ID_BASE(16+16),
+        .STAT_UPDATE_PERIOD(1024)
     )
     sfp_mac_inst (
         .xcvr_ctrl_clk(clk),
@@ -554,7 +630,7 @@ end else begin : sfp_mac
          */
         .stat_clk(clk),
         .stat_rst(rst),
-        .m_axis_stat(axis_sfp_stat),
+        .m_axis_stat(axis_eth_stat[1]),
 
         /*
          * Status

example/KCU105/fpga/tb/fpga_core/Makefile

@@ -21,7 +21,9 @@ TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += ../../rtl/$(DUT).sv
 VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
 VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f
+VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
+VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
+VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
 VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
 VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
 VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv

example/KCU105/fpga/tb/fpga_core/test_fpga_core.py

@@ -77,8 +77,8 @@ class TB:
                 self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
                 self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
 
-        self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1)
+        self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
-        self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1)
+        self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
 
         dut.phy_gmii_clk_en.setimmediatevalue(1)
 
@@ -117,25 +117,6 @@ class TB:
             await RisingEdge(self.dut.clk)
 
 
-async def uart_test(tb, source, sink):
-    tb.log.info("Test UART")
-
-    tx_data = b"FPGA Ninja"
-
-    tb.log.info("UART TX: %s", tx_data)
-
-    await source.write(tx_data)
-
-    rx_data = bytearray()
-
-    while len(rx_data) < len(tx_data):
-        rx_data.extend(await sink.read())
-
-    tb.log.info("UART RX: %s", rx_data)
-
-    tb.log.info("UART test done")
-
-
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
@@ -227,10 +208,6 @@ async def run_test(dut):
 
     tests = []
 
-    tb.log.info("Start UART test")
-
-    tests.append(cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink)))
-
     tb.log.info("Start BASE-T MAC loopback test")
 
     tests.append(cocotb.start_soon(mac_test(tb, tb.gmii_source, tb.gmii_sink)))
@@ -279,7 +256,9 @@ def test_fpga_core(request, sfp_rate):
         os.path.join(rtl_dir, f"{dut}.sv"),
         os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"),
         os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
-        os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"),
+        os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"),
+        os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"),
+        os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"),
         os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
         os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
         os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"),