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example/KR260: Add example design for KR260
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
537
example/KR260/fpga/rtl/fpga.sv
Normal file
537
example/KR260/fpga/rtl/fpga.sv
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@@ -0,0 +1,537 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "zynquplus",
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// Use 90 degree clock for RGMII transmit
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parameter logic USE_CLK90 = 1'b1
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)
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(
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/*
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* Clock: 25MHz
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*/
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input wire logic clk_25mhz,
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/*
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* GPIO
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*/
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output wire logic [1:0] led,
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output wire logic [1:0] sfp_led,
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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input wire logic phy2_rx_clk,
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input wire logic [3:0] phy2_rxd,
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input wire logic phy2_rx_ctl,
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output wire logic phy2_tx_clk,
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output wire logic [3:0] phy2_txd,
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output wire logic phy2_tx_ctl,
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output wire logic phy2_reset_n,
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input wire logic phy3_rx_clk,
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input wire logic [3:0] phy3_rxd,
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input wire logic phy3_rx_ctl,
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output wire logic phy3_tx_clk,
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output wire logic [3:0] phy3_txd,
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output wire logic phy3_tx_ctl,
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output wire logic phy3_reset_n,
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/*
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* Ethernet: SFP+
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*/
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input wire logic sfp_rx_p,
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input wire logic sfp_rx_n,
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output wire logic sfp_tx_p,
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output wire logic sfp_tx_n,
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input wire logic sfp_mgt_refclk_p,
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input wire logic sfp_mgt_refclk_n,
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output wire logic sfp_tx_disable,
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input wire logic sfp_tx_fault,
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input wire logic sfp_rx_los,
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input wire logic sfp_mod_abs,
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inout wire logic sfp_i2c_scl,
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inout wire logic sfp_i2c_sda
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);
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// Clock and reset
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk90_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire clk90_125mhz_int;
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wire rst_125mhz_int;
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// Internal 62.5 MHz clock
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wire clk_62mhz_mmcm_out;
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wire clk_62mhz_int;
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// Internal 312.5 MHz clock
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wire clk_312mhz_mmcm_out;
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wire clk_312mhz_int;
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wire rst_312mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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MMCME3_BASE #(
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// 25 MHz input
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.CLKIN1_PERIOD(40),
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.REF_JITTER1(0.010),
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// 25 MHz input / 1 = 25 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 25 MHz PFD * 50 = 1250 MHz VCO (range 600 MHz to 1440 MHz)
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.CLKFBOUT_MULT_F(50),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 90 degrees
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.CLKOUT1_DIVIDE(10),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(90),
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// 1250 MHz / 20 = 62.5 MHz, 0 degrees
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.CLKOUT2_DIVIDE(20),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// 1250 MHz / 4 = 312.5 MHz, 0 degrees
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.CLKOUT3_DIVIDE(4),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 25 MHz input
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.CLKIN1(clk_25mhz),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// 125 MHz, 90 degrees
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.CLKOUT1(clk90_125mhz_mmcm_out),
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.CLKOUT1B(),
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// 62.5 MHz, 0 degrees
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.CLKOUT2(clk_62mhz_mmcm_out),
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.CLKOUT2B(),
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// 312.5 MHz, 0 degrees
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.CLKOUT3(clk_312mhz_mmcm_out),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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BUFG
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clk90_125mhz_bufg_inst (
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.I(clk90_125mhz_mmcm_out),
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.O(clk90_125mhz_int)
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);
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BUFG
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clk_62mhz_bufg_inst (
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.I(clk_62mhz_mmcm_out),
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.O(clk_62mhz_int)
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);
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BUFG
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clk_312mhz_bufg_inst (
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.I(clk_312mhz_mmcm_out),
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.O(clk_312mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_312mhz_inst (
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.clk(clk_312mhz_int),
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.rst(~mmcm_locked),
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.out(rst_312mhz_int)
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);
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// GPIO
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wire sfp_tx_fault_int;
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wire sfp_rx_los_int;
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wire sfp_mod_abs_int;
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wire sfp_i2c_scl_i;
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wire sfp_i2c_scl_o;
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wire sfp_i2c_scl_t;
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wire sfp_i2c_sda_i;
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wire sfp_i2c_sda_o;
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wire sfp_i2c_sda_t;
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reg sfp_i2c_scl_o_reg;
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reg sfp_i2c_scl_t_reg;
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reg sfp_i2c_sda_o_reg;
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reg sfp_i2c_sda_t_reg;
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always @(posedge clk_125mhz_int) begin
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sfp_i2c_scl_o_reg <= sfp_i2c_scl_o;
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sfp_i2c_scl_t_reg <= sfp_i2c_scl_t;
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sfp_i2c_sda_o_reg <= sfp_i2c_sda_o;
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sfp_i2c_sda_t_reg <= sfp_i2c_sda_t;
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end
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taxi_sync_signal #(
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.WIDTH(5),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({sfp_tx_fault, sfp_rx_los, sfp_mod_abs, sfp_i2c_scl, sfp_i2c_sda}),
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.out({sfp_tx_fault_int, sfp_rx_los_int, sfp_mod_abs_int, sfp_i2c_scl_i, sfp_i2c_sda_i})
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);
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assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg;
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assign sfp_i2c_sda = sfp_i2c_sda_t_reg ? 1'bz : sfp_i2c_sda_o_reg;
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// IODELAY elements for RGMII interface to PHY
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wire [3:0] phy2_rxd_int;
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wire phy2_rx_ctl_int;
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wire [3:0] phy3_rxd_int;
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wire phy3_rx_ctl_int;
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IDELAYCTRL #(
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.SIM_DEVICE("ULTRASCALE")
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)
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idelayctrl_inst (
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.REFCLK(clk_312mhz_int),
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.RST(rst_312mhz_int),
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.RDY()
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);
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for (genvar n = 0; n < 4; n = n + 1) begin : phy2_rxd_idelay_bit
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IDELAYE3 #(
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.DELAY_SRC("IDATAIN"),
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.CASCADE("NONE"),
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.DELAY_TYPE("FIXED"),
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.DELAY_VALUE(0),
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.REFCLK_FREQUENCY(312.5),
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.DELAY_FORMAT("TIME"),
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.UPDATE_MODE("SYNC"),
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.SIM_DEVICE("ULTRASCALE_PLUS")
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)
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idelay_inst (
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.CASC_IN(1'b0),
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.CASC_RETURN(1'b0),
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.CASC_OUT(),
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.IDATAIN(phy2_rxd[n]),
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.DATAIN(1'b0),
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.DATAOUT(phy2_rxd_int[n]),
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.CLK(1'b0),
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.EN_VTC(1'b1),
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.CE(1'b0),
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.INC(1'b0),
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.LOAD(1'b0),
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.RST(1'b0),
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.CNTVALUEIN(9'd0),
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.CNTVALUEOUT()
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);
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end
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IDELAYE3 #(
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.DELAY_SRC("IDATAIN"),
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.CASCADE("NONE"),
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.DELAY_TYPE("FIXED"),
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.DELAY_VALUE(0),
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.REFCLK_FREQUENCY(312.5),
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.DELAY_FORMAT("TIME"),
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.UPDATE_MODE("SYNC"),
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.SIM_DEVICE("ULTRASCALE_PLUS")
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)
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phy2_rx_ctl_idelay (
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.CASC_IN(1'b0),
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.CASC_RETURN(1'b0),
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.CASC_OUT(),
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.IDATAIN(phy2_rx_ctl),
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.DATAIN(1'b0),
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.DATAOUT(phy2_rx_ctl_int),
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.CLK(1'b0),
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.EN_VTC(1'b1),
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.CE(1'b0),
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.INC(1'b0),
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.LOAD(1'b0),
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.RST(1'b0),
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.CNTVALUEIN(9'd0),
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.CNTVALUEOUT()
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);
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for (genvar n = 0; n < 4; n = n + 1) begin : phy3_rxd_idelay_bit
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IDELAYE3 #(
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.DELAY_SRC("IDATAIN"),
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.CASCADE("NONE"),
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.DELAY_TYPE("FIXED"),
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.DELAY_VALUE(0),
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.REFCLK_FREQUENCY(312.5),
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.DELAY_FORMAT("TIME"),
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.UPDATE_MODE("SYNC"),
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.SIM_DEVICE("ULTRASCALE_PLUS")
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)
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idelay_inst (
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.CASC_IN(1'b0),
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.CASC_RETURN(1'b0),
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.CASC_OUT(),
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.IDATAIN(phy3_rxd[n]),
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.DATAIN(1'b0),
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.DATAOUT(phy3_rxd_int[n]),
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.CLK(1'b0),
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.EN_VTC(1'b1),
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.CE(1'b0),
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.INC(1'b0),
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.LOAD(1'b0),
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.RST(1'b0),
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.CNTVALUEIN(9'd0),
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.CNTVALUEOUT()
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);
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end
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IDELAYE3 #(
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.DELAY_SRC("IDATAIN"),
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.CASCADE("NONE"),
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.DELAY_TYPE("FIXED"),
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.DELAY_VALUE(0),
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.REFCLK_FREQUENCY(312.5),
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.DELAY_FORMAT("TIME"),
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.UPDATE_MODE("SYNC"),
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.SIM_DEVICE("ULTRASCALE_PLUS")
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)
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phy3_rx_ctl_idelay (
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.CASC_IN(1'b0),
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.CASC_RETURN(1'b0),
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.CASC_OUT(),
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.IDATAIN(phy3_rx_ctl),
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.DATAIN(1'b0),
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.DATAOUT(phy3_rx_ctl_int),
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.CLK(1'b0),
|
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.EN_VTC(1'b1),
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.CE(1'b0),
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.INC(1'b0),
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.LOAD(1'b0),
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.RST(1'b0),
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.CNTVALUEIN(9'd0),
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.CNTVALUEOUT()
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);
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// 1000BASE-X SFP
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wire sfp_gmii_clk_int;
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wire sfp_gmii_rst_int;
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wire sfp_gmii_clk_en_int;
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wire [7:0] sfp_gmii_txd_int;
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wire sfp_gmii_tx_en_int;
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wire sfp_gmii_tx_er_int;
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wire [7:0] sfp_gmii_rxd_int;
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wire sfp_gmii_rx_dv_int;
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wire sfp_gmii_rx_er_int;
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wire sfp_gmii_txuserclk2;
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wire sfp_gmii_resetdone;
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assign sfp_gmii_clk_int = sfp_gmii_txuserclk2;
|
||||
|
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taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_sfp_inst (
|
||||
.clk(sfp_gmii_clk_int),
|
||||
.rst(rst_125mhz_int || !sfp_gmii_resetdone),
|
||||
.out(sfp_gmii_rst_int)
|
||||
);
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||||
|
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wire [15:0] sfp_status_vect;
|
||||
|
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wire sfp_status_link_status = sfp_status_vect[0];
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wire sfp_status_link_synchronization = sfp_status_vect[1];
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wire sfp_status_rudi_c = sfp_status_vect[2];
|
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wire sfp_status_rudi_i = sfp_status_vect[3];
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wire sfp_status_rudi_invalid = sfp_status_vect[4];
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wire sfp_status_rxdisperr = sfp_status_vect[5];
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wire sfp_status_rxnotintable = sfp_status_vect[6];
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wire sfp_status_phy_link_status = sfp_status_vect[7];
|
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wire [1:0] sfp_status_remote_fault_encdg = sfp_status_vect[9:8];
|
||||
wire [1:0] sfp_status_speed = sfp_status_vect[11:10];
|
||||
wire sfp_status_duplex = sfp_status_vect[12];
|
||||
wire sfp_status_remote_fault = sfp_status_vect[13];
|
||||
wire [1:0] sfp_status_pause = sfp_status_vect[15:14];
|
||||
|
||||
wire [4:0] sfp_config_vect;
|
||||
|
||||
assign sfp_config_vect[4] = 1'b0; // autonegotiation enable
|
||||
assign sfp_config_vect[3] = 1'b0; // isolate
|
||||
assign sfp_config_vect[2] = 1'b0; // power down
|
||||
assign sfp_config_vect[1] = 1'b0; // loopback enable
|
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assign sfp_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
basex_pcs_pma_0
|
||||
sfp_pcspma (
|
||||
.gtrefclk_p(sfp_mgt_refclk_p),
|
||||
.gtrefclk_n(sfp_mgt_refclk_n),
|
||||
.gtrefclk_out(),
|
||||
.txn(sfp_tx_n),
|
||||
.txp(sfp_tx_p),
|
||||
.rxn(sfp_rx_n),
|
||||
.rxp(sfp_rx_p),
|
||||
.independent_clock_bufg(clk_62mhz_int),
|
||||
.userclk_out(),
|
||||
.userclk2_out(sfp_gmii_txuserclk2),
|
||||
.rxuserclk_out(),
|
||||
.rxuserclk2_out(),
|
||||
.gtpowergood(),
|
||||
.resetdone(sfp_gmii_resetdone),
|
||||
.pma_reset_out(),
|
||||
.mmcm_locked_out(),
|
||||
.gmii_txd(sfp_gmii_txd_int),
|
||||
.gmii_tx_en(sfp_gmii_tx_en_int),
|
||||
.gmii_tx_er(sfp_gmii_tx_er_int),
|
||||
.gmii_rxd(sfp_gmii_rxd_int),
|
||||
.gmii_rx_dv(sfp_gmii_rx_dv_int),
|
||||
.gmii_rx_er(sfp_gmii_rx_er_int),
|
||||
.gmii_isolate(),
|
||||
.configuration_vector(sfp_config_vect),
|
||||
.status_vector(sfp_status_vect),
|
||||
.reset(rst_125mhz_int),
|
||||
.signal_detect(1'b1)
|
||||
);
|
||||
|
||||
assign sfp_gmii_clk_en_int = 1'b1;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_125mhz_int),
|
||||
.clk90(clk90_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.led(led),
|
||||
.sfp_led(sfp_led),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T RGMII
|
||||
*/
|
||||
.phy2_rgmii_rx_clk(phy2_rx_clk),
|
||||
.phy2_rgmii_rxd(phy2_rxd_int),
|
||||
.phy2_rgmii_rx_ctl(phy2_rx_ctl_int),
|
||||
.phy2_rgmii_tx_clk(phy2_tx_clk),
|
||||
.phy2_rgmii_txd(phy2_txd),
|
||||
.phy2_rgmii_tx_ctl(phy2_tx_ctl),
|
||||
.phy2_reset_n(phy2_reset_n),
|
||||
|
||||
.phy3_rgmii_rx_clk(phy3_rx_clk),
|
||||
.phy3_rgmii_rxd(phy3_rxd_int),
|
||||
.phy3_rgmii_rx_ctl(phy3_rx_ctl_int),
|
||||
.phy3_rgmii_tx_clk(phy3_tx_clk),
|
||||
.phy3_rgmii_txd(phy3_txd),
|
||||
.phy3_rgmii_tx_ctl(phy3_tx_ctl),
|
||||
.phy3_reset_n(phy3_reset_n),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-X SFP
|
||||
*/
|
||||
.sfp_gmii_clk(sfp_gmii_clk_int),
|
||||
.sfp_gmii_rst(sfp_gmii_rst_int),
|
||||
.sfp_gmii_clk_en(sfp_gmii_clk_en_int),
|
||||
.sfp_gmii_rxd(sfp_gmii_rxd_int),
|
||||
.sfp_gmii_rx_dv(sfp_gmii_rx_dv_int),
|
||||
.sfp_gmii_rx_er(sfp_gmii_rx_er_int),
|
||||
.sfp_gmii_txd(sfp_gmii_txd_int),
|
||||
.sfp_gmii_tx_en(sfp_gmii_tx_en_int),
|
||||
.sfp_gmii_tx_er(sfp_gmii_tx_er_int),
|
||||
.sfp_tx_disable(sfp_tx_disable),
|
||||
.sfp_tx_fault(sfp_tx_fault_int),
|
||||
.sfp_rx_los(sfp_rx_los_int),
|
||||
.sfp_mod_abs(sfp_mod_abs_int),
|
||||
.sfp_i2c_scl_i(sfp_i2c_scl_i),
|
||||
.sfp_i2c_scl_o(sfp_i2c_scl_o),
|
||||
.sfp_i2c_scl_t(sfp_i2c_scl_t),
|
||||
.sfp_i2c_sda_i(sfp_i2c_sda_i),
|
||||
.sfp_i2c_sda_o(sfp_i2c_sda_o),
|
||||
.sfp_i2c_sda_t(sfp_i2c_sda_t)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
296
example/KR260/fpga/rtl/fpga_core.sv
Normal file
296
example/KR260/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,296 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter FAMILY = "zynquplus",
|
||||
// Use 90 degree clock for RGMII transmit
|
||||
parameter logic USE_CLK90 = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic clk90,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] led,
|
||||
output wire logic [1:0] sfp_led,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T
|
||||
*/
|
||||
input wire logic phy2_rgmii_rx_clk,
|
||||
input wire logic [3:0] phy2_rgmii_rxd,
|
||||
input wire logic phy2_rgmii_rx_ctl,
|
||||
output wire logic phy2_rgmii_tx_clk,
|
||||
output wire logic [3:0] phy2_rgmii_txd,
|
||||
output wire logic phy2_rgmii_tx_ctl,
|
||||
output wire logic phy2_reset_n,
|
||||
|
||||
input wire logic phy3_rgmii_rx_clk,
|
||||
input wire logic [3:0] phy3_rgmii_rxd,
|
||||
input wire logic phy3_rgmii_rx_ctl,
|
||||
output wire logic phy3_rgmii_tx_clk,
|
||||
output wire logic [3:0] phy3_rgmii_txd,
|
||||
output wire logic phy3_rgmii_tx_ctl,
|
||||
output wire logic phy3_reset_n,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-X SFP
|
||||
*/
|
||||
input wire logic sfp_gmii_clk,
|
||||
input wire logic sfp_gmii_rst,
|
||||
input wire logic sfp_gmii_clk_en,
|
||||
input wire logic [7:0] sfp_gmii_rxd,
|
||||
input wire logic sfp_gmii_rx_dv,
|
||||
input wire logic sfp_gmii_rx_er,
|
||||
output wire logic [7:0] sfp_gmii_txd,
|
||||
output wire logic sfp_gmii_tx_en,
|
||||
output wire logic sfp_gmii_tx_er,
|
||||
|
||||
output wire logic sfp_tx_disable,
|
||||
input wire logic sfp_tx_fault,
|
||||
input wire logic sfp_rx_los,
|
||||
input wire logic sfp_mod_abs,
|
||||
input wire logic sfp_i2c_scl_i,
|
||||
output wire logic sfp_i2c_scl_o,
|
||||
output wire logic sfp_i2c_scl_t,
|
||||
input wire logic sfp_i2c_sda_i,
|
||||
output wire logic sfp_i2c_sda_o,
|
||||
output wire logic sfp_i2c_sda_t
|
||||
);
|
||||
|
||||
// BASE-T PHY
|
||||
assign phy2_reset_n = !rst;
|
||||
assign phy3_reset_n = !rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_phy2_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_phy2_tx_cpl();
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_phy3_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_phy3_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_rgmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
phy2_eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_clk90(clk90),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_phy2_eth),
|
||||
.m_axis_tx_cpl(axis_phy2_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_phy2_eth),
|
||||
|
||||
/*
|
||||
* RGMII interface
|
||||
*/
|
||||
.rgmii_rx_clk(phy2_rgmii_rx_clk),
|
||||
.rgmii_rxd(phy2_rgmii_rxd),
|
||||
.rgmii_rx_ctl(phy2_rgmii_rx_ctl),
|
||||
.rgmii_tx_clk(phy2_rgmii_tx_clk),
|
||||
.rgmii_txd(phy2_rgmii_txd),
|
||||
.rgmii_tx_ctl(phy2_rgmii_tx_ctl),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
taxi_eth_mac_1g_rgmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
phy3_eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_clk90(clk90),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_phy3_eth),
|
||||
.m_axis_tx_cpl(axis_phy3_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_phy3_eth),
|
||||
|
||||
/*
|
||||
* RGMII interface
|
||||
*/
|
||||
.rgmii_rx_clk(phy3_rgmii_rx_clk),
|
||||
.rgmii_rxd(phy3_rgmii_rxd),
|
||||
.rgmii_rx_ctl(phy3_rgmii_rx_ctl),
|
||||
.rgmii_tx_clk(phy3_rgmii_tx_clk),
|
||||
.rgmii_txd(phy3_rgmii_txd),
|
||||
.rgmii_tx_ctl(phy3_rgmii_tx_ctl),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
// SFP+
|
||||
assign sfp_tx_disable = 1'b0;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
sfp_eth_mac_inst (
|
||||
.rx_clk(sfp_gmii_clk),
|
||||
.rx_rst(sfp_gmii_rst),
|
||||
.tx_clk(sfp_gmii_clk),
|
||||
.tx_rst(sfp_gmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_sfp_eth),
|
||||
.m_axis_tx_cpl(axis_sfp_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_sfp_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(sfp_gmii_rxd),
|
||||
.gmii_rx_dv(sfp_gmii_rx_dv),
|
||||
.gmii_rx_er(sfp_gmii_rx_er),
|
||||
.gmii_txd(sfp_gmii_txd),
|
||||
.gmii_tx_en(sfp_gmii_tx_en),
|
||||
.gmii_tx_er(sfp_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(sfp_gmii_clk_en),
|
||||
.tx_clk_enable(sfp_gmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user