mirror of
https://github.com/fpganinja/taxi.git
synced 2026-04-08 13:08:42 -07:00
cndm: Initial commit of board control I2C logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
50
src/cndm/tb/cndm_brd_ctrl_i2c/Makefile
Normal file
50
src/cndm/tb/cndm_brd_ctrl_i2c/Makefile
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@@ -0,0 +1,50 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ns
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = cndm_brd_ctrl_i2c
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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# export PARAM_DEFAULT_PRESCALE := 1
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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382
src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.py
Normal file
382
src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.py
Normal file
@@ -0,0 +1,382 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import struct
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
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from cocotbext.axi.utils import hexdump_str
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from cocotbext.i2c import I2cMemory
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CMD_BRD_OP_NOP = 0x0000
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CMD_BRD_OP_FLASH_RD = 0x0100
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CMD_BRD_OP_FLASH_WR = 0x0101
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CMD_BRD_OP_FLASH_CMD = 0x0108
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CMD_BRD_OP_EEPROM_RD = 0x0200
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CMD_BRD_OP_EEPROM_WR = 0x0201
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CMD_BRD_OP_OPTIC_RD = 0x0300
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CMD_BRD_OP_OPTIC_WR = 0x0301
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CMD_BRD_OP_HWID_SN_RD = 0x0400
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CMD_BRD_OP_HWID_VPD_RD = 0x0410
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CMD_BRD_OP_HWID_MAC_RD = 0x0480
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CMD_BRD_OP_PLL_STATUS_RD = 0x0500
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CMD_BRD_OP_PLL_TUNE_RAW_RD = 0x0502
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CMD_BRD_OP_PLL_TUNE_RAW_WR = 0x0503
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CMD_BRD_OP_PLL_TUNE_PPT_RD = 0x0504
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CMD_BRD_OP_PLL_TUNE_PPT_WR = 0x0505
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CMD_BRD_OP_I2C_RD = 0x8100
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CMD_BRD_OP_I2C_WR = 0x8101
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
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self.brd_ctrl_cmd = AxiStreamSource(AxiStreamBus(dut.s_axis_cmd), dut.clk, dut.rst)
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self.brd_ctrl_rsp = AxiStreamSink(AxiStreamBus(dut.m_axis_rsp), dut.clk, dut.rst)
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self.i2c_eeprom = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
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scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x54, size=256)
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self.sfp0 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
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scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x50, size=256)
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self.sfp1 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
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scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x51, size=256)
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self.si570 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
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scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x5D, size=256)
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self.mux1 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
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scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x74, size=256)
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self.mux2 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
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scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x75, size=256)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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@cocotb.test()
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async def run_test(dut):
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tb = TB(dut)
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await tb.reset()
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tb.i2c_eeprom.write_mem(0, bytes.fromhex("""
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37 35 37 35 31 39 32 37 31 37 33 32 2d 36 39 39
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39 36 20 20 20 20 20 20 20 20 20 20 20 20 20 20
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00 0a 35 03 72 c9 00 00 00 00 00 00 00 00 00 00
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54 53 53 30 31 36 35 2d 30 32 20 20 20 20 20 20
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5b 31 31 31 31 31 31 31 31 31 5d 20 20 20 20 20
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57 65 64 2c 20 31 36 20 41 75 67 20 32 30 31 37
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31 30 3a 33 35 3a 35 36 2b 30 38 30 30 20 20 20
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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4b 43 55 31 30 35 20 20 20 20 20 20 20 20 20 20
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31 2e 31 20 20 20 20 20 20 20 20 20 20 20 20 20
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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"""))
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tb.sfp0.write_mem(0, bytes.fromhex("""
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03 04 21 00 00 00 00 00 04 00 00 00 67 00 00 00
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00 00 03 00 41 6d 70 68 65 6e 6f 6c 20 20 20 20
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20 20 20 20 00 41 50 48 35 37 31 35 34 30 30 30
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32 20 20 20 20 20 20 20 4b 20 20 20 01 00 00 f7
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00 00 00 00 41 50 46 30 39 34 38 30 30 32 30 32
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37 39 20 20 30 39 31 31 32 34 20 20 00 00 00 c1
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00
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""" + " ff"*128))
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tb.sfp1.write_mem(0, bytes.fromhex("""
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03 04 21 00 00 00 00 00 04 00 00 00 67 00 00 00
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00 00 03 00 41 6d 70 68 65 6e 6f 6c 20 20 20 20
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20 20 20 20 00 41 50 48 35 37 31 35 34 30 30 30
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32 20 20 20 20 20 20 20 4b 20 20 20 01 00 00 f7
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00 00 00 00 41 50 46 30 39 34 38 30 30 32 30 32
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37 39 20 20 30 39 31 31 32 34 20 20 00 00 00 c1
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00
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""" + " ff"*128))
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tb.si570.write_mem(0, bytes.fromhex("""
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4f 02 32 a1 3d 20 00 01 c2 bb ff 84 82 07 c2 c0
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00 00 00 00 c2 c0 00 00 00 07 c2 c0 00 00 00 0c
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b9 09 80 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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20 7f 86 81 7b 81 03 00 10 08 00 00 00 00 02 bb
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ff 84 82 00 00 00 62 00 00 00 00 00 00 00 00 00
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"""))
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tb.log.info("Read MAC")
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cmd = struct.pack("<HHLbbbbLLL",
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0, # index
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CMD_BRD_OP_HWID_MAC_RD, # opcode
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0, # flags
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0, # page
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0, # bank
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0, # dev addr offset
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0, # rsvd
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0, # addr
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0, # len
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0, # rsvd
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)
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await tb.brd_ctrl_cmd.send(cmd)
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rsp = await tb.brd_ctrl_rsp.recv()
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tb.log.info("Response: %s", rsp)
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tb.log.info("MAC: %s", ':'.join(x.hex() for x in struct.unpack_from('6c', rsp.tdata, 24+2)))
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tb.log.info("Read SN")
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cmd = struct.pack("<HHLbbbbLLL",
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0, # index
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CMD_BRD_OP_HWID_SN_RD, # opcode
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0, # flags
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0, # page
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0, # bank
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0, # dev addr offset
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0, # rsvd
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0, # addr
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0, # len
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0, # rsvd
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)
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await tb.brd_ctrl_cmd.send(cmd)
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rsp = await tb.brd_ctrl_rsp.recv()
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tb.log.info("Response: %s", rsp)
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tb.log.info("SN: %s", rsp.tdata[24:24+32].strip(b' \x00'))
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tb.log.info("Read EEPROM")
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cmd = struct.pack("<HHLbbbbLLL",
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0, # index
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CMD_BRD_OP_EEPROM_RD, # opcode
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0, # flags
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0, # page
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0, # bank
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0, # dev addr offset
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0, # rsvd
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0x00, # addr
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32, # len
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0, # rsvd
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)
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await tb.brd_ctrl_cmd.send(cmd)
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rsp = await tb.brd_ctrl_rsp.recv()
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tb.log.info("Response: %s", rsp)
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tb.log.info("Data: %s", rsp.tdata[24:24+32])
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tb.log.info("Read SFP0")
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cmd = struct.pack("<HHLbbbbLLL",
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0, # index
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CMD_BRD_OP_OPTIC_RD, # opcode
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0, # flags
|
||||
0, # page
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0, # bank
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0, # dev addr offset
|
||||
0, # rsvd
|
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0x00, # addr
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32, # len
|
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0, # rsvd
|
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)
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await tb.brd_ctrl_cmd.send(cmd)
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rsp = await tb.brd_ctrl_rsp.recv()
|
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|
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tb.log.info("Response: %s", rsp)
|
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tb.log.info("Data: %s", rsp.tdata[24:24+32])
|
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tb.log.info("Read SFP1")
|
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cmd = struct.pack("<HHLbbbbLLL",
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1, # index
|
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CMD_BRD_OP_OPTIC_RD, # opcode
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0, # flags
|
||||
0, # page
|
||||
0, # bank
|
||||
0, # dev addr offset
|
||||
0, # rsvd
|
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0x00, # addr
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||||
32, # len
|
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0, # rsvd
|
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)
|
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|
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await tb.brd_ctrl_cmd.send(cmd)
|
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rsp = await tb.brd_ctrl_rsp.recv()
|
||||
|
||||
tb.log.info("Response: %s", rsp)
|
||||
tb.log.info("Data: %s", rsp.tdata[24:24+32])
|
||||
|
||||
tb.log.info("Write EEPROM")
|
||||
data = b"EEPROM write data"
|
||||
|
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cmd = struct.pack("<HHLbbbbLLL",
|
||||
0, # index
|
||||
CMD_BRD_OP_EEPROM_WR, # opcode
|
||||
0, # flags
|
||||
0, # page
|
||||
0, # bank
|
||||
0, # dev addr offset
|
||||
0, # rsvd
|
||||
0x80, # addr
|
||||
len(data), # len
|
||||
0, # rsvd
|
||||
)+data
|
||||
|
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await tb.brd_ctrl_cmd.send(cmd)
|
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rsp = await tb.brd_ctrl_rsp.recv()
|
||||
|
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tb.log.info("Response: %s", rsp)
|
||||
|
||||
tb.log.info("Write SFP0")
|
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data = b"SFP0 write data"
|
||||
|
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cmd = struct.pack("<HHLbbbbLLL",
|
||||
0, # index
|
||||
CMD_BRD_OP_OPTIC_WR, # opcode
|
||||
0, # flags
|
||||
0, # page
|
||||
0, # bank
|
||||
0, # dev addr offset
|
||||
0, # rsvd
|
||||
0x80, # addr
|
||||
len(data), # len
|
||||
0, # rsvd
|
||||
)+data
|
||||
|
||||
await tb.brd_ctrl_cmd.send(cmd)
|
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rsp = await tb.brd_ctrl_rsp.recv()
|
||||
|
||||
tb.log.info("Response: %s", rsp)
|
||||
|
||||
tb.log.info("Write SFP1")
|
||||
data = b"SFP1 write data"
|
||||
|
||||
cmd = struct.pack("<HHLbbbbLLL",
|
||||
1, # index
|
||||
CMD_BRD_OP_OPTIC_WR, # opcode
|
||||
0, # flags
|
||||
0, # page
|
||||
0, # bank
|
||||
0, # dev addr offset
|
||||
0, # rsvd
|
||||
0x80, # addr
|
||||
len(data), # len
|
||||
0, # rsvd
|
||||
)+data
|
||||
|
||||
await tb.brd_ctrl_cmd.send(cmd)
|
||||
rsp = await tb.brd_ctrl_rsp.recv()
|
||||
|
||||
tb.log.info("Response: %s", rsp)
|
||||
|
||||
for k in range(1000):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.log.info("EEPROM data:")
|
||||
tb.log.info(hexdump_str(tb.i2c_eeprom.mem, 0, 256))
|
||||
|
||||
tb.log.info("PLL data:")
|
||||
tb.log.info(hexdump_str(tb.si570.mem, 0, 256))
|
||||
|
||||
tb.log.info("SFP0 data:")
|
||||
tb.log.info(hexdump_str(tb.sfp0.mem, 0, 256))
|
||||
|
||||
tb.log.info("SFP1 data:")
|
||||
tb.log.info(hexdump_str(tb.sfp1.mem, 0, 256))
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_cndm_brd_ctrl_i2c(request):
|
||||
dut = "cndm_brd_ctrl_i2c"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
131
src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.sv
Normal file
131
src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.sv
Normal file
@@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* I2C master testbench
|
||||
*/
|
||||
module test_cndm_brd_ctrl_i2c #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter logic OPTIC_EN = 1'b1,
|
||||
parameter OPTIC_CNT = 2,
|
||||
|
||||
parameter logic EEPROM_EN = 1'b1,
|
||||
parameter EEPROM_IDX = OPTIC_EN ? OPTIC_CNT : 0,
|
||||
|
||||
parameter logic MAC_EEPROM_EN = EEPROM_EN,
|
||||
parameter MAC_EEPROM_IDX = EEPROM_IDX,
|
||||
parameter MAC_EEPROM_OFFSET = 32,
|
||||
parameter MAC_COUNT = OPTIC_CNT,
|
||||
parameter logic MAC_FROM_BASE = 1'b1,
|
||||
|
||||
parameter logic SN_EEPROM_EN = EEPROM_EN,
|
||||
parameter SN_EEPROM_IDX = EEPROM_IDX,
|
||||
parameter SN_EEPROM_OFFSET = 0,
|
||||
parameter SN_LEN = 32,
|
||||
|
||||
parameter logic PLL_EN = 1'b1,
|
||||
parameter PLL_IDX = EEPROM_IDX + (EEPROM_EN ? 1 : 0),
|
||||
|
||||
parameter logic MUX_EN = 1'b1,
|
||||
parameter MUX_CNT = 2,
|
||||
parameter logic [MUX_CNT-1:0][6:0] MUX_I2C_ADDR = {7'h75, 7'h74},
|
||||
|
||||
parameter DEV_CNT = PLL_IDX + (PLL_EN ? 1 : 0),
|
||||
parameter logic [DEV_CNT-1:0][6:0] DEV_I2C_ADDR = {7'h5D, 7'h54, 7'h51, 7'h50},
|
||||
parameter logic [DEV_CNT-1:0][31:0] DEV_ADDR_CFG = {32'h00_00_0000, 32'h00_00_0040, 32'h7e_7f_0070, 32'h7e_7f_0070},
|
||||
parameter logic [DEV_CNT-1:0][MUX_CNT-1:0][7:0] DEV_MUX_MASK = {{8'h00, 8'h01}, {8'h07, 8'h00}, {8'h00, 8'h08}, {8'h00, 8'h04}},
|
||||
|
||||
parameter I2C_PRESCALE = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(32),
|
||||
.KEEP_EN(1),
|
||||
.ID_EN(1),
|
||||
.ID_W(4),
|
||||
.USER_EN(1),
|
||||
.USER_W(1)
|
||||
) s_axis_cmd(), m_axis_rsp();
|
||||
|
||||
logic i2c_scl_i;
|
||||
logic i2c_scl_o;
|
||||
logic i2c_sda_i;
|
||||
logic i2c_sda_o;
|
||||
|
||||
logic [DEV_CNT-1:0] dev_sel;
|
||||
logic [DEV_CNT-1:0] dev_rst;
|
||||
|
||||
cndm_brd_ctrl_i2c #(
|
||||
.OPTIC_EN(OPTIC_EN),
|
||||
.OPTIC_CNT(OPTIC_CNT),
|
||||
|
||||
.EEPROM_EN(EEPROM_EN),
|
||||
.EEPROM_IDX(EEPROM_IDX),
|
||||
|
||||
.MAC_EEPROM_EN(MAC_EEPROM_EN),
|
||||
.MAC_EEPROM_IDX(MAC_EEPROM_IDX),
|
||||
.MAC_EEPROM_OFFSET(MAC_EEPROM_OFFSET),
|
||||
.MAC_COUNT(MAC_COUNT),
|
||||
.MAC_FROM_BASE(MAC_FROM_BASE),
|
||||
|
||||
.SN_EEPROM_EN(SN_EEPROM_EN),
|
||||
.SN_EEPROM_IDX(SN_EEPROM_IDX),
|
||||
.SN_EEPROM_OFFSET(SN_EEPROM_OFFSET),
|
||||
.SN_LEN(SN_LEN),
|
||||
|
||||
.PLL_EN(PLL_EN),
|
||||
.PLL_IDX(PLL_IDX),
|
||||
|
||||
.MUX_EN(MUX_EN),
|
||||
.MUX_CNT(MUX_CNT),
|
||||
.MUX_I2C_ADDR(MUX_I2C_ADDR),
|
||||
|
||||
.DEV_CNT(DEV_CNT),
|
||||
.DEV_I2C_ADDR(DEV_I2C_ADDR),
|
||||
.DEV_ADDR_CFG(DEV_ADDR_CFG),
|
||||
.DEV_MUX_MASK(DEV_MUX_MASK),
|
||||
|
||||
.I2C_PRESCALE(I2C_PRESCALE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* Board control command interface
|
||||
*/
|
||||
.s_axis_cmd(s_axis_cmd),
|
||||
.m_axis_rsp(m_axis_rsp),
|
||||
|
||||
/*
|
||||
* I2C interface
|
||||
*/
|
||||
.i2c_scl_i(i2c_scl_i),
|
||||
.i2c_scl_o(i2c_scl_o),
|
||||
.i2c_sda_i(i2c_sda_i),
|
||||
.i2c_sda_o(i2c_sda_o),
|
||||
|
||||
.dev_sel(dev_sel),
|
||||
.dev_rst(dev_rst)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user