eth: Minor cleanup

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/rtl/taxi_eth_phy_10g_tx_if.sv

@@ -39,6 +39,7 @@ module taxi_eth_phy_10g_tx_if #
     output wire logic               tx_gbx_req_sync,
     output wire logic               tx_gbx_req_stall,
     input  wire logic               tx_gbx_sync = 1'b0,
+
     /*
      * SERDES interface
      */

src/eth/rtl/taxi_eth_phy_1g_basex_rx.sv

@@ -81,7 +81,7 @@ rx_if_inst (
     .rst(rst),
 
     /*
-     * 1000GBASE-X encoded interface
+     * 1000BASE-X encoded interface
      */
     .encoded_rx_data(encoded_rx_data),
     .encoded_rx_data_k(encoded_rx_data_k),
@@ -121,7 +121,7 @@ dec_inst (
     .rst(rst),
 
     /*
-     * 1000GBASE-X encoded input
+     * 1000BASE-X encoded input
      */
     .encoded_rx_data(encoded_rx_data),
     .encoded_rx_data_k(encoded_rx_data_k),

src/eth/rtl/taxi_eth_phy_1g_basex_rx_if.sv

@@ -31,7 +31,7 @@ module taxi_eth_phy_1g_basex_rx_if #
     input  wire logic               rst,
 
     /*
-     * 10GBASE-R encoded interface
+     * 1000BASE-X encoded interface
      */
     output wire logic [DATA_W-1:0]  encoded_rx_data,
     output wire logic [CTRL_W-1:0]  encoded_rx_data_k,
@@ -42,7 +42,7 @@ module taxi_eth_phy_1g_basex_rx_if #
      */
     input  wire logic [DATA_W-1:0]  serdes_rx_data,
     input  wire logic [CTRL_W-1:0]  serdes_rx_data_k,
-    input  wire logic               serdes_rx_data_valid,
+    input  wire logic               serdes_rx_data_valid = 1'b1,
     output wire logic               serdes_rx_reset_req,
 
     /*

src/eth/rtl/taxi_eth_phy_1g_basex_tx.sv

@@ -86,7 +86,7 @@ enc_inst (
     .tx_gbx_sync_in(tx_gbx_sync),
 
     /*
-     * 1000GBASE-X encoded interface
+     * 1000BASE-X encoded interface
      */
     .encoded_tx_data(encoded_tx_data),
     .encoded_tx_data_k(encoded_tx_data_k),
@@ -110,7 +110,7 @@ tx_if_inst (
     .rst(rst),
 
     /*
-     * 1000GBASE-X encoded interface
+     * 1000BASE-X encoded interface
      */
     .encoded_tx_data(encoded_tx_data),
     .encoded_tx_data_k(encoded_tx_data_k),

src/eth/rtl/taxi_eth_phy_1g_basex_tx_if.sv

@@ -30,7 +30,7 @@ module taxi_eth_phy_1g_basex_tx_if #
     input  wire logic               rst,
 
     /*
-     * 10GBASE-R encoded interface
+     * 1000BASE-X encoded interface
      */
     input  wire logic [DATA_W-1:0]  encoded_tx_data,
     input  wire logic [CTRL_W-1:0]  encoded_tx_data_k,