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https://github.com/fpganinja/taxi.git
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io: Add generic IDDR and ODDR modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
157
rtl/io/taxi_iddr.sv
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157
rtl/io/taxi_iddr.sv
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@@ -0,0 +1,157 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic IDDR module
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*/
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module taxi_iddr #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic clk,
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input wire logic [WIDTH-1:0] d,
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output wire logic [WIDTH-1:0] q1,
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output wire logic [WIDTH-1:0] q2
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);
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/*
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Provides a consistent input DDR flip flop across multiple FPGA families
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_____ _____ _____ _____ ____
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clk ____/ \_____/ \_____/ \_____/ \_____/
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_ _____ _____ _____ _____ _____ _____ _____ _____ _____ _
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d _X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7__X_D8__X_
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_______ ___________ ___________ ___________ ___________ _
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q1 _______X___________X____D0_____X____D2_____X____D4_____X_
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_______ ___________ ___________ ___________ ___________ _
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q2 _______X___________X____D1_____X____D3_____X____D5_____X_
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*/
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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if (FAMILY == "spartan6") begin
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// spartan6 uses IODDR2
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for (genvar n = 0; n < WIDTH; n = n + 1) begin : iddr
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wire q1_int;
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logic q1_delay = 1'b0;
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IDDR2 #(
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.DDR_ALIGNMENT("C0")
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)
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iddr_inst (
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.Q0(q1_int),
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.Q1(q2[n]),
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.C0(clk),
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.C1(~clk),
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.CE(1'b1),
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.D(d[n]),
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.R(1'b0),
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.S(1'b0)
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);
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always_ff @(posedge clk) begin
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q1_delay <= q1_int;
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end
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assign q1[n] = q1_delay;
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end
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end else begin
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// virtex4, virtex5, virtex6, virtex7, kintex7, artix7, virtexu, kintexu, virtexuplus, kintexuplus
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for (genvar n = 0; n < WIDTH; n = n + 1) begin : iddr
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IDDR #(
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.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
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.SRTYPE("ASYNC")
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)
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iddr_inst (
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.Q1(q1[n]),
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.Q2(q2[n]),
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.C(clk),
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.CE(1'b1),
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.D(d[n]),
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.R(1'b0),
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.S(1'b0)
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);
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end
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end
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end else if (!SIM && VENDOR == "ALTERA") begin
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// Altera/Intel/Altera device support
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wire [WIDTH-1:0] q1_int;
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logic [WIDTH-1:0] q1_delay = '0;
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altddio_in #(
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.WIDTH(WIDTH),
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.POWER_UP_HIGH("OFF")
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)
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altddio_in_inst (
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.aset(1'b0),
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.datain(d),
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.inclocken(1'b1),
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.inclock(clk),
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.aclr(1'b0),
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.dataout_h(q1_int),
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.dataout_l(q2)
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);
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always_ff @(posedge clk) begin
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q1_delay <= q1_int;
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end
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assign q1 = q1_delay;
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end else begin
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// generic/simulation implementation (no vendor primitives)
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logic [WIDTH-1:0] d_reg_1 = '0;
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logic [WIDTH-1:0] d_reg_2 = '0;
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logic [WIDTH-1:0] q_reg_1 = '0;
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logic [WIDTH-1:0] q_reg_2 = '0;
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always_ff @(posedge clk) begin
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d_reg_1 <= d;
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end
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always_ff @(negedge clk) begin
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d_reg_2 <= d;
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end
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always_ff @(posedge clk) begin
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q_reg_1 <= d_reg_1;
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q_reg_2 <= d_reg_2;
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end
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assign q1 = q_reg_1;
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assign q2 = q_reg_2;
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end
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endmodule
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`resetall
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139
rtl/io/taxi_oddr.sv
Normal file
139
rtl/io/taxi_oddr.sv
Normal file
@@ -0,0 +1,139 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic ODDR module
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*/
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module taxi_oddr #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic clk,
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input wire logic [WIDTH-1:0] d1,
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input wire logic [WIDTH-1:0] d2,
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output wire logic [WIDTH-1:0] q
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);
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/*
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Provides a consistent output DDR flip flop across multiple FPGA families
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_____ _____ _____ _____
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clk ____/ \_____/ \_____/ \_____/ \_____
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_ ___________ ___________ ___________ ___________ __
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d1 _X____D0_____X____D2_____X____D4_____X____D6_____X__
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_ ___________ ___________ ___________ ___________ __
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d2 _X____D1_____X____D3_____X____D5_____X____D7_____X__
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_____ _____ _____ _____ _____ _____ _____ _____ ____
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d _____X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7_
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*/
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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if (FAMILY == "spartan6") begin
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// spartan6 uses IODDR2
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for (genvar n = 0; n < WIDTH; n = n + 1) begin : oddr
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ODDR2 #(
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.DDR_ALIGNMENT("C0"),
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.SRTYPE("ASYNC")
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)
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oddr_inst (
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.Q(q[n]),
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.C0(clk),
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.C1(~clk),
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.CE(1'b1),
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.D0(d1[n]),
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.D1(d2[n]),
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.R(1'b0),
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.S(1'b0)
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);
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end
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end else begin
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// virtex4, virtex5, virtex6, virtex7, kintex7, artix7, virtexu, kintexu, virtexuplus, kintexuplus
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for (genvar n = 0; n < WIDTH; n = n + 1) begin : oddr
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ODDR #(
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.DDR_CLK_EDGE("SAME_EDGE"),
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.SRTYPE("ASYNC")
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)
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oddr_inst (
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.Q(q[n]),
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.C(clk),
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.CE(1'b1),
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.D1(d1[n]),
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.D2(d2[n]),
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.R(1'b0),
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.S(1'b0)
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);
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end
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end
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end else if (!SIM && VENDOR == "ALTERA") begin
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// Altera/Intel/Altera device support
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altddio_out #(
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.WIDTH(WIDTH),
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.POWER_UP_HIGH("OFF"),
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.OE_REG("UNUSED")
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)
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altddio_out_inst (
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.aset(1'b0),
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.datain_h(d1),
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.datain_l(d2),
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.outclocken(1'b1),
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.outclock(clk),
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.aclr(1'b0),
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.dataout(q)
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);
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end else begin
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// generic/simulation implementation (no vendor primitives)
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logic [WIDTH-1:0] d_reg_1 = '0;
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logic [WIDTH-1:0] d_reg_2 = '0;
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logic [WIDTH-1:0] q_reg = '0;
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always_ff @(posedge clk) begin
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d_reg_1 <= d1;
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d_reg_2 <= d2;
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end
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always_ff @(posedge clk) begin
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q_reg <= d1;
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end
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always_ff @(negedge clk) begin
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q_reg <= d_reg_2;
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end
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assign q = q_reg;
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end
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endmodule
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`resetall
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