bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 08:58:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

example/KR260: Update readme

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-20 10:21:49 -08:00
parent 650da9c972
commit e388cb22c6
1 changed files with 1 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
example/KR260/fpga/README.md
View File

@@ -4,10 +4,8 @@
This example design targets the Xilinx KR260 FPGA board.
The design places looped-back MACs on the BASE-T ports and SFP+ cage, as well as a looped-back UART on on the USB UART connection.
The design places looped-back MACs on the BASE-T ports and SFP+ cage.
* USB UART
* Looped-back UART
* RJ-45 Ethernet ports with TI DP83867CSRGZ PHY
* Looped-back MAC via RGMII
* SFP+ cage