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example/KR260: Update readme

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-20 10:21:49 -08:00
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example/KR260/fpga/README.md
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This example design targets the Xilinx KR260 FPGA board. This example design targets the Xilinx KR260 FPGA board.
The design places looped-back MACs on the BASE-T ports and SFP+ cage, as well as a looped-back UART on on the USB UART connection. The design places looped-back MACs on the BASE-T ports and SFP+ cage.
* USB UART
* Looped-back UART
* RJ-45 Ethernet ports with TI DP83867CSRGZ PHY * RJ-45 Ethernet ports with TI DP83867CSRGZ PHY
* Looped-back MAC via RGMII * Looped-back MAC via RGMII
* SFP+ cage * SFP+ cage