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eth: Use shift registers for AN match counts

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-06-18 12:40:11 -07:00
parent dd0b0c616c
commit e39ac2fd9c
3 changed files with 65 additions and 83 deletions
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46
src/eth/rtl/taxi_axis_basex_rx_16.sv
View File

@@ -167,9 +167,9 @@ logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
logic [15:0] rx_an_cfg_reg = '0;
logic rx_an_cfg_valid_reg = 1'b0;
logic [1:0] an_ability_match_cnt_reg = '0;
logic [1:0] an_ack_match_cnt_reg = '0;
logic [1:0] an_idle_match_cnt_reg = '0;
logic [1:0] an_ability_match_reg = '0;
logic [1:0] an_ack_match_reg = '0;
logic [1:0] an_idle_match_reg = '0;
logic start_packet_int_reg = 1'b0;
logic [1:0] start_packet_reg = '0;
@@ -223,9 +223,9 @@ end
assign rx_an_cfg = AN_EN ? rx_an_cfg_reg : '0;
assign rx_an_cfg_valid = AN_EN ? rx_an_cfg_valid_reg : 1'b0;
assign rx_an_ability_match = AN_EN ? an_ability_match_cnt_reg[1] : 1'b0;
assign rx_an_ack_match = AN_EN ? an_ack_match_cnt_reg[1] : 1'b0;
assign rx_an_idle_match = AN_EN ? an_idle_match_cnt_reg[1] : 1'b0;
assign rx_an_ability_match = AN_EN ? an_ability_match_reg[1] : 1'b0;
assign rx_an_ack_match = AN_EN ? an_ack_match_reg[1] : 1'b0;
assign rx_an_idle_match = AN_EN ? an_idle_match_reg[1] : 1'b0;
assign rx_start_packet = start_packet_reg;
@@ -670,11 +670,9 @@ always_ff @(posedge clk) begin
end
if (AN_EN && input_i_d0_reg) begin
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
if (!(&an_idle_match_cnt_reg)) begin
an_idle_match_cnt_reg <= an_idle_match_cnt_reg + 1;
end
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= {an_idle_match_reg[0], 1'b1};
end
// config symbol detection
@@ -686,20 +684,16 @@ always_ff @(posedge clk) begin
rx_an_cfg_reg <= encoded_rx_data;
rx_an_cfg_valid_reg <= encoded_rx_data_k == 2'b00;
if (((rx_an_cfg_reg ^ encoded_rx_data) & 16'h4000) == 0) begin
if (!(&an_ability_match_cnt_reg)) begin
an_ability_match_cnt_reg <= an_ability_match_cnt_reg + 1;
end
an_ability_match_reg <= {an_ability_match_reg[0], 1'b1};
end else begin
an_ability_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
end
if (rx_an_cfg_reg[14] && rx_an_cfg_reg == encoded_rx_data) begin
if (!(&an_ack_match_cnt_reg)) begin
an_ack_match_cnt_reg <= an_ack_match_cnt_reg + 1;
end
an_ack_match_reg <= {an_ack_match_reg[0], 1'b1};
end else begin
an_ack_match_cnt_reg <= '0;
an_ack_match_reg <= '0;
end
an_idle_match_cnt_reg <= '0;
an_idle_match_reg <= '0;
end
// start control character detection
@@ -710,9 +704,9 @@ always_ff @(posedge clk) begin
end
if (AN_EN && input_start_d0_reg) begin
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
an_idle_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= '0;
end
// SFD detection
@@ -764,9 +758,9 @@ always_ff @(posedge clk) begin
m_axis_rx_tvalid_reg <= 1'b0;
rx_an_cfg_valid_reg <= 1'b0;
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
an_idle_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= '0;
start_packet_int_reg <= 1'b0;
start_packet_reg <= '0;

48
src/eth/rtl/taxi_axis_basex_rx_8.sv
View File

@@ -165,9 +165,9 @@ logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
logic [15:0] rx_an_cfg_reg = '0;
logic rx_an_cfg_valid_reg = 1'b0;
logic an_cfg_match_reg = 1'b0;
logic [1:0] an_ability_match_cnt_reg = '0;
logic [1:0] an_ack_match_cnt_reg = '0;
logic [1:0] an_idle_match_cnt_reg = '0;
logic [1:0] an_ability_match_reg = '0;
logic [1:0] an_ack_match_reg = '0;
logic [1:0] an_idle_match_reg = '0;
logic start_packet_int_reg = 1'b0;
logic start_packet_reg = 1'b0;
@@ -207,9 +207,9 @@ end
assign rx_an_cfg = AN_EN ? rx_an_cfg_reg : '0;
assign rx_an_cfg_valid = AN_EN ? rx_an_cfg_valid_reg : 1'b0;
assign rx_an_ability_match = AN_EN ? an_ability_match_cnt_reg[1] : 1'b0;
assign rx_an_ack_match = AN_EN ? an_ack_match_cnt_reg[1] : 1'b0;
assign rx_an_idle_match = AN_EN ? an_idle_match_cnt_reg[1] : 1'b0;
assign rx_an_ability_match = AN_EN ? an_ability_match_reg[1] : 1'b0;
assign rx_an_ack_match = AN_EN ? an_ack_match_reg[1] : 1'b0;
assign rx_an_idle_match = AN_EN ? an_idle_match_reg[1] : 1'b0;
assign rx_start_packet = start_packet_reg;
@@ -530,11 +530,9 @@ always_ff @(posedge clk) begin
end
if (AN_EN && input_i_d0_reg) begin
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
if (!(&an_idle_match_cnt_reg)) begin
an_idle_match_cnt_reg <= an_idle_match_cnt_reg + 1;
end
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= {an_idle_match_reg[0], 1'b1};
end
// config symbol detection
@@ -546,27 +544,23 @@ always_ff @(posedge clk) begin
rx_an_cfg_reg[7:0] <= encoded_rx_data;
an_cfg_match_reg <= rx_an_cfg_reg[7:0] == encoded_rx_data;
input_c_d1_reg <= encoded_rx_data_k == 1'b0;
an_idle_match_cnt_reg <= '0;
an_idle_match_reg <= '0;
end
if (AN_EN && input_c_d1_reg) begin
rx_an_cfg_reg[15:8] <= encoded_rx_data;
rx_an_cfg_valid_reg <= encoded_rx_data_k == 1'b0;
if (an_cfg_match_reg && ((rx_an_cfg_reg[15:8] ^ encoded_rx_data) & 8'h40) == 0) begin
if (!(&an_ability_match_cnt_reg)) begin
an_ability_match_cnt_reg <= an_ability_match_cnt_reg + 1;
end
an_ability_match_reg <= {an_ability_match_reg[0], 1'b1};
end else begin
an_ability_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
end
if (an_cfg_match_reg && rx_an_cfg_reg[14] && rx_an_cfg_reg[15:8] == encoded_rx_data) begin
if (!(&an_ack_match_cnt_reg)) begin
an_ack_match_cnt_reg <= an_ack_match_cnt_reg + 1;
end
an_ack_match_reg <= {an_ack_match_reg[0], 1'b1};
end else begin
an_ack_match_cnt_reg <= '0;
an_ack_match_reg <= '0;
end
an_idle_match_cnt_reg <= '0;
an_idle_match_reg <= '0;
end
// start control character detection
@@ -575,9 +569,9 @@ always_ff @(posedge clk) begin
end
if (AN_EN && input_start_d0_reg) begin
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
an_idle_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= '0;
end
if (reset_crc) begin
@@ -615,9 +609,9 @@ always_ff @(posedge clk) begin
m_axis_rx_tvalid_reg <= 1'b0;
rx_an_cfg_valid_reg <= 1'b0;
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
an_idle_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= '0;
start_packet_int_reg <= 1'b0;
start_packet_reg <= 1'b0;

54
src/eth/rtl/taxi_gmii_basex_dec.sv
View File

@@ -105,9 +105,9 @@ logic gmii_rx_valid_reg = '0, gmii_rx_valid_next;
logic [15:0] rx_an_cfg_reg = '0, rx_an_cfg_next;
logic rx_an_cfg_valid_reg = 1'b0, rx_an_cfg_valid_next;
logic an_cfg_match_reg = 1'b0, an_cfg_match_next;
logic [1:0] an_ability_match_cnt_reg = '0, an_ability_match_cnt_next;
logic [1:0] an_ack_match_cnt_reg = '0, an_ack_match_cnt_next;
logic [1:0] an_idle_match_cnt_reg = '0, an_idle_match_cnt_next;
logic [1:0] an_ability_match_reg = '0, an_ability_match_next;
logic [1:0] an_ack_match_reg = '0, an_ack_match_next;
logic [1:0] an_idle_match_reg = '0, an_idle_match_next;
logic stat_rx_err_bad_block_reg = '0, stat_rx_err_bad_block_next;
logic stat_rx_err_framing_reg = '0, stat_rx_err_framing_next;
@@ -119,9 +119,9 @@ assign gmii_rx_valid = gmii_rx_valid_reg;
assign rx_an_cfg = AN_EN ? rx_an_cfg_reg : '0;
assign rx_an_cfg_valid = AN_EN ? rx_an_cfg_valid_reg : 1'b0;
assign rx_an_ability_match = AN_EN ? an_ability_match_cnt_reg[1] : 1'b0;
assign rx_an_ack_match = AN_EN ? an_ack_match_cnt_reg[1] : 1'b0;
assign rx_an_idle_match = AN_EN ? an_idle_match_cnt_reg[1] : 1'b0;
assign rx_an_ability_match = AN_EN ? an_ability_match_reg[1] : 1'b0;
assign rx_an_ack_match = AN_EN ? an_ack_match_reg[1] : 1'b0;
assign rx_an_idle_match = AN_EN ? an_idle_match_reg[1] : 1'b0;
assign stat_rx_err_bad_block = stat_rx_err_bad_block_reg;
assign stat_rx_err_framing = stat_rx_err_framing_reg;
@@ -140,9 +140,9 @@ always_comb begin
rx_an_cfg_next = rx_an_cfg_reg;
rx_an_cfg_valid_next = 1'b0;
an_cfg_match_next = an_cfg_match_reg;
an_ability_match_cnt_next = an_ability_match_cnt_reg;
an_ack_match_cnt_next = an_ack_match_cnt_reg;
an_idle_match_cnt_next = an_idle_match_cnt_reg;
an_ability_match_next = an_ability_match_reg;
an_ack_match_next = an_ack_match_reg;
an_idle_match_next = an_idle_match_reg;
stat_rx_err_bad_block_next = 1'b0;
stat_rx_err_framing_next = 1'b0;
@@ -202,11 +202,9 @@ always_comb begin
gmii_rx_er_next[seg] = 1'b0;
end else if (AN_EN && k28p5_cyc && (encoded_rx_data[seg*8 +: 8] == D(5,6) || encoded_rx_data[seg*8 +: 8] == D(16,2))) begin
// I1/I2
an_ability_match_cnt_next = '0;
an_ack_match_cnt_next = '0;
if (!(&an_idle_match_cnt_next)) begin
an_idle_match_cnt_next = an_idle_match_cnt_next + 1;
end
an_ability_match_next = '0;
an_ack_match_next = '0;
an_idle_match_next = {an_idle_match_next[0], 1'b1};
end else if (AN_EN && k28p5_cyc && (encoded_rx_data[seg*8 +: 8] == D(21,5) || encoded_rx_data[seg*8 +: 8] == D(2,2))) begin
// C1/C2
c_cyc = 1'b1;
@@ -214,25 +212,21 @@ always_comb begin
if (!odd_cyc) begin
rx_an_cfg_next[7:0] = encoded_rx_data[seg*8 +: 8];
an_cfg_match_next = rx_an_cfg_next[7:0] == encoded_rx_data[seg*8 +: 8];
an_idle_match_cnt_next = '0;
an_idle_match_next = '0;
end else begin
rx_an_cfg_next[15:8] = encoded_rx_data[seg*8 +: 8];
rx_an_cfg_valid_next = 1'b1;
if (an_cfg_match_next && ((rx_an_cfg_next[15:8] ^ encoded_rx_data[seg*8 +: 8]) & 8'h40) == 0) begin
if (!(&an_ability_match_cnt_next)) begin
an_ability_match_cnt_next = an_ability_match_cnt_next + 1;
end
an_ability_match_next = {an_ability_match_next[0], 1'b1};
end else begin
an_ability_match_cnt_next = '0;
an_ability_match_next = '0;
end
if (an_cfg_match_next && rx_an_cfg_next[14] && rx_an_cfg_next[15:8] == encoded_rx_data[seg*8 +: 8]) begin
if (!(&an_ack_match_cnt_next)) begin
an_ack_match_cnt_next = an_ack_match_cnt_next + 1;
end
an_ack_match_next = {an_ack_match_next[0], 1'b1};
end else begin
an_ack_match_cnt_next = '0;
an_ack_match_next = '0;
end
an_idle_match_cnt_next = '0;
an_idle_match_next = '0;
c_cyc = 1'b0;
end
end
@@ -271,9 +265,9 @@ always_ff @(posedge clk) begin
rx_an_cfg_reg <= rx_an_cfg_next;
rx_an_cfg_valid_reg <= rx_an_cfg_valid_next;
an_cfg_match_reg <= an_cfg_match_next;
an_ability_match_cnt_reg <= an_ability_match_cnt_next;
an_ack_match_cnt_reg <= an_ack_match_cnt_next;
an_idle_match_cnt_reg <= an_idle_match_cnt_next;
an_ability_match_reg <= an_ability_match_next;
an_ack_match_reg <= an_ack_match_next;
an_idle_match_reg <= an_idle_match_next;
stat_rx_err_bad_block_reg <= stat_rx_err_bad_block_next;
stat_rx_err_framing_reg <= stat_rx_err_framing_next;
@@ -290,9 +284,9 @@ always_ff @(posedge clk) begin
gmii_rx_valid_reg <= 1'b0;
rx_an_cfg_valid_reg <= 1'b0;
an_ability_match_cnt_reg <= '0;
an_ack_match_cnt_reg <= '0;
an_idle_match_cnt_reg <= '0;
an_ability_match_reg <= '0;
an_ack_match_reg <= '0;
an_idle_match_reg <= '0;
stat_rx_err_bad_block_reg <= 1'b0;
stat_rx_err_framing_reg <= 1'b0;