axi: Add AXI FIFO module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-30 22:17:53 -07:00
parent 0080125120
commit e87e16c299
8 changed files with 1267 additions and 0 deletions

View File

@@ -29,6 +29,7 @@ To facilitate the dual-license model, contributions to the project can only be a
* AXI to AXI lite adapter
* Register slice
* Width converter
* Synchronous FIFO
* Single-port RAM
* AXI lite
* SV interface for AXI lite