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eth: Add MAC statistics module to 1G MACs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-08 20:22:53 -07:00
parent bb90cd5a08
commit e90340db6e
33 changed files with 1453 additions and 192 deletions
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1
rtl/eth/taxi_eth_mac_1g.f
View File

@@ -1,6 +1,7 @@
taxi_eth_mac_1g.sv
taxi_axis_gmii_rx.sv
taxi_axis_gmii_tx.sv
taxi_eth_mac_stats.f
taxi_mac_ctrl_tx.sv
taxi_mac_ctrl_rx.sv
taxi_mac_pause_ctrl_tx.sv

194
rtl/eth/taxi_eth_mac_1g.sv
View File

@@ -23,7 +23,12 @@ module taxi_eth_mac_1g #
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
)
(
input wire logic rx_clk,
@@ -91,14 +96,45 @@ module taxi_eth_mac_1g #
input wire logic rx_mii_select = 1'b0,
input wire logic tx_mii_select = 1'b0,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
output wire logic tx_start_packet,
output wire logic tx_error_underflow,
output wire logic stat_tx_byte,
output wire logic [15:0] stat_tx_pkt_len,
output wire logic stat_tx_pkt_ucast,
output wire logic stat_tx_pkt_mcast,
output wire logic stat_tx_pkt_bcast,
output wire logic stat_tx_pkt_vlan,
output wire logic stat_tx_pkt_good,
output wire logic stat_tx_pkt_bad,
output wire logic stat_tx_err_oversize,
output wire logic stat_tx_err_user,
output wire logic stat_tx_err_underflow,
output wire logic rx_start_packet,
output wire logic rx_error_bad_frame,
output wire logic rx_error_bad_fcs,
output wire logic stat_rx_byte,
output wire logic [15:0] stat_rx_pkt_len,
output wire logic stat_rx_pkt_fragment,
output wire logic stat_rx_pkt_jabber,
output wire logic stat_rx_pkt_ucast,
output wire logic stat_rx_pkt_mcast,
output wire logic stat_rx_pkt_bcast,
output wire logic stat_rx_pkt_vlan,
output wire logic stat_rx_pkt_good,
output wire logic stat_rx_pkt_bad,
output wire logic stat_rx_err_oversize,
output wire logic stat_rx_err_bad_fcs,
output wire logic stat_rx_err_bad_block,
output wire logic stat_rx_err_framing,
output wire logic stat_rx_err_preamble,
input wire logic stat_rx_fifo_drop = 1'b0,
output wire logic stat_tx_mcf,
output wire logic stat_rx_mcf,
output wire logic stat_tx_lfc_pkt,
@@ -121,8 +157,10 @@ module taxi_eth_mac_1g #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1,
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
@@ -202,28 +240,28 @@ axis_gmii_rx_inst (
/*
* Configuration
*/
.cfg_rx_max_pkt_len(16'd9218),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
/*
* Status
*/
.rx_start_packet(rx_start_packet),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(rx_error_bad_frame),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(rx_error_bad_fcs),
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble()
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble)
);
taxi_axis_gmii_tx #(
@@ -265,28 +303,112 @@ axis_gmii_tx_inst (
/*
* Configuration
*/
.cfg_tx_max_pkt_len(16'd9218),
.cfg_tx_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(tx_error_underflow)
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow)
);
generate
if (STAT_EN) begin : stats
taxi_eth_mac_stats #(
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.INC_W(1)
)
mac_stats_inst (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
.stat_tx_lfc_xon(stat_tx_lfc_xon),
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
.stat_tx_lfc_paused(stat_tx_lfc_paused),
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
.stat_tx_pfc_xon(stat_tx_pfc_xon),
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
.stat_tx_pfc_paused(stat_tx_pfc_paused),
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
.stat_rx_lfc_xon(stat_rx_lfc_xon),
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
.stat_rx_lfc_paused(stat_rx_lfc_paused),
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
.stat_rx_pfc_xon(stat_rx_pfc_xon),
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
.stat_rx_pfc_paused(stat_rx_pfc_paused)
);
end else begin
assign m_axis_stat.tdata = '0;
assign m_axis_stat.tkeep = '0;
assign m_axis_stat.tlast = '0;
assign m_axis_stat.tvalid = '0;
assign m_axis_stat.tid = '0;
assign m_axis_stat.tdest = '0;
assign m_axis_stat.tuser = '0;
end
if (MAC_CTRL_EN) begin : mac_ctrl
@@ -603,8 +725,6 @@ end else begin
end
endgenerate
endmodule
`resetall

69
rtl/eth/taxi_eth_mac_1g_fifo.sv
View File

@@ -20,6 +20,11 @@ module taxi_eth_mac_1g_fifo #
parameter DATA_W = 8,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -71,6 +76,13 @@ module taxi_eth_mac_1g_fifo #
input wire logic rx_mii_select = 1'b0,
input wire logic tx_mii_select = 1'b0,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
@@ -87,8 +99,10 @@ module taxi_eth_mac_1g_fifo #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1
);
@@ -164,13 +178,20 @@ always_ff @(posedge logic_clk or posedge logic_rst) begin
end
end
wire stat_rx_fifo_drop;
taxi_eth_mac_1g #(
.DATA_W(DATA_W),
.PADDING_EN(PADDING_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(1'b0),
.PFC_EN(1'b0),
.PAUSE_EN(1'b0)
.PAUSE_EN(1'b0),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
@@ -238,14 +259,46 @@ eth_mac_1g_inst (
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
// .rx_error_bad_frame(rx_error_bad_frame_int),
.tx_start_packet(),
.tx_error_underflow(tx_error_underflow_int),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(tx_error_underflow_int),
.rx_start_packet(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -268,8 +321,10 @@ eth_mac_1g_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
@@ -432,7 +487,7 @@ rx_fifo (
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_overflow(stat_rx_fifo_drop),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),

96
rtl/eth/taxi_eth_mac_1g_gmii.sv
View File

@@ -25,7 +25,12 @@ module taxi_eth_mac_1g_gmii #
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
)
(
input wire logic gtx_clk,
@@ -90,14 +95,45 @@ module taxi_eth_mac_1g_gmii #
input wire logic tx_pause_req = 1'b0,
output wire logic tx_pause_ack,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
output wire logic tx_start_packet,
output wire logic tx_error_underflow,
output wire logic stat_tx_byte,
output wire logic [15:0] stat_tx_pkt_len,
output wire logic stat_tx_pkt_ucast,
output wire logic stat_tx_pkt_mcast,
output wire logic stat_tx_pkt_bcast,
output wire logic stat_tx_pkt_vlan,
output wire logic stat_tx_pkt_good,
output wire logic stat_tx_pkt_bad,
output wire logic stat_tx_err_oversize,
output wire logic stat_tx_err_user,
output wire logic stat_tx_err_underflow,
output wire logic rx_start_packet,
output wire logic rx_error_bad_frame,
output wire logic rx_error_bad_fcs,
output wire logic stat_rx_byte,
output wire logic [15:0] stat_rx_pkt_len,
output wire logic stat_rx_pkt_fragment,
output wire logic stat_rx_pkt_jabber,
output wire logic stat_rx_pkt_ucast,
output wire logic stat_rx_pkt_mcast,
output wire logic stat_rx_pkt_bcast,
output wire logic stat_rx_pkt_vlan,
output wire logic stat_rx_pkt_good,
output wire logic stat_rx_pkt_bad,
output wire logic stat_rx_err_oversize,
output wire logic stat_rx_err_bad_fcs,
output wire logic stat_rx_err_bad_block,
output wire logic stat_rx_err_framing,
output wire logic stat_rx_err_preamble,
input wire logic stat_rx_fifo_drop = 1'b0,
output wire logic [1:0] link_speed,
output wire logic stat_tx_mcf,
output wire logic stat_rx_mcf,
@@ -121,8 +157,10 @@ module taxi_eth_mac_1g_gmii #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1,
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
@@ -301,7 +339,12 @@ taxi_eth_mac_1g #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
@@ -369,14 +412,45 @@ eth_mac_1g_inst (
.rx_mii_select(rx_mii_select_sync),
.tx_mii_select(tx_mii_select_sync),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
@@ -399,8 +473,10 @@ eth_mac_1g_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

69
rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv
View File

@@ -22,6 +22,11 @@ module taxi_eth_mac_1g_gmii_fifo #
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -66,6 +71,13 @@ module taxi_eth_mac_1g_gmii_fifo #
output wire logic gmii_tx_en,
output wire logic gmii_tx_er,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
@@ -83,8 +95,10 @@ module taxi_eth_mac_1g_gmii_fifo #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1
);
@@ -177,6 +191,8 @@ always @(posedge logic_clk) begin
link_speed_sync_reg_2 <= link_speed_sync_reg_1;
end
wire stat_rx_fifo_drop;
taxi_eth_mac_1g_gmii #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -185,7 +201,12 @@ taxi_eth_mac_1g_gmii #(
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(1'b0),
.PFC_EN(1'b0),
.PAUSE_EN(1'b0)
.PAUSE_EN(1'b0),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_1g_gmii_inst (
.gtx_clk(gtx_clk),
@@ -250,14 +271,46 @@ eth_mac_1g_gmii_inst (
.tx_pause_req(0),
.tx_pause_ack(),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
// .rx_error_bad_frame(rx_error_bad_frame_int),
.tx_start_packet(),
.tx_error_underflow(tx_error_underflow_int),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(tx_error_underflow_int),
.rx_start_packet(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.link_speed(link_speed_int),
.stat_tx_mcf(),
.stat_rx_mcf(),
@@ -281,8 +334,10 @@ eth_mac_1g_gmii_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
@@ -445,7 +500,7 @@ rx_fifo (
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_overflow(stat_rx_fifo_drop),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),

96
rtl/eth/taxi_eth_mac_1g_rgmii.sv
View File

@@ -26,7 +26,12 @@ module taxi_eth_mac_1g_rgmii #
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
)
(
input wire logic gtx_clk,
@@ -89,14 +94,45 @@ module taxi_eth_mac_1g_rgmii #
input wire logic tx_pause_req = 1'b0,
output wire logic tx_pause_ack,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
output wire logic tx_start_packet,
output wire logic tx_error_underflow,
output wire logic stat_tx_byte,
output wire logic [15:0] stat_tx_pkt_len,
output wire logic stat_tx_pkt_ucast,
output wire logic stat_tx_pkt_mcast,
output wire logic stat_tx_pkt_bcast,
output wire logic stat_tx_pkt_vlan,
output wire logic stat_tx_pkt_good,
output wire logic stat_tx_pkt_bad,
output wire logic stat_tx_err_oversize,
output wire logic stat_tx_err_user,
output wire logic stat_tx_err_underflow,
output wire logic rx_start_packet,
output wire logic rx_error_bad_frame,
output wire logic rx_error_bad_fcs,
output wire logic stat_rx_byte,
output wire logic [15:0] stat_rx_pkt_len,
output wire logic stat_rx_pkt_fragment,
output wire logic stat_rx_pkt_jabber,
output wire logic stat_rx_pkt_ucast,
output wire logic stat_rx_pkt_mcast,
output wire logic stat_rx_pkt_bcast,
output wire logic stat_rx_pkt_vlan,
output wire logic stat_rx_pkt_good,
output wire logic stat_rx_pkt_bad,
output wire logic stat_rx_err_oversize,
output wire logic stat_rx_err_bad_fcs,
output wire logic stat_rx_err_bad_block,
output wire logic stat_rx_err_framing,
output wire logic stat_rx_err_preamble,
input wire logic stat_rx_fifo_drop = 1'b0,
output wire logic [1:0] link_speed,
output wire logic stat_tx_mcf,
output wire logic stat_rx_mcf,
@@ -120,8 +156,10 @@ module taxi_eth_mac_1g_rgmii #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1,
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
@@ -301,7 +339,12 @@ taxi_eth_mac_1g #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
@@ -369,14 +412,45 @@ eth_mac_1g_inst (
.rx_mii_select(rx_mii_select_sync),
.tx_mii_select(tx_mii_select_sync),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
@@ -399,8 +473,10 @@ eth_mac_1g_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

69
rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv
View File

@@ -23,6 +23,11 @@ module taxi_eth_mac_1g_rgmii_fifo #
parameter logic USE_CLK90 = 1'b1,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -65,6 +70,13 @@ module taxi_eth_mac_1g_rgmii_fifo #
output wire logic [3:0] rgmii_txd,
output wire logic rgmii_tx_ctl,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
@@ -82,8 +94,10 @@ module taxi_eth_mac_1g_rgmii_fifo #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1
);
@@ -176,6 +190,8 @@ always @(posedge logic_clk) begin
link_speed_sync_reg_2 <= link_speed_sync_reg_1;
end
wire stat_rx_fifo_drop;
taxi_eth_mac_1g_rgmii #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -185,7 +201,12 @@ taxi_eth_mac_1g_rgmii #(
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(1'b0),
.PFC_EN(1'b0),
.PAUSE_EN(1'b0)
.PAUSE_EN(1'b0),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_1g_rgmii_inst (
.gtx_clk(gtx_clk),
@@ -248,14 +269,46 @@ eth_mac_1g_rgmii_inst (
.tx_pause_req(0),
.tx_pause_ack(),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
// .rx_error_bad_frame(rx_error_bad_frame_int),
.tx_start_packet(),
.tx_error_underflow(tx_error_underflow_int),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(tx_error_underflow_int),
.rx_start_packet(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.link_speed(link_speed_int),
.stat_tx_mcf(),
.stat_rx_mcf(),
@@ -279,8 +332,10 @@ eth_mac_1g_rgmii_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
@@ -443,7 +498,7 @@ rx_fifo (
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_overflow(stat_rx_fifo_drop),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),

96
rtl/eth/taxi_eth_mac_mii.sv
View File

@@ -25,7 +25,12 @@ module taxi_eth_mac_mii #
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
)
(
input wire logic rst,
@@ -88,14 +93,45 @@ module taxi_eth_mac_mii #
input wire logic tx_pause_req = 1'b0,
output wire logic tx_pause_ack,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
output wire logic tx_start_packet,
output wire logic tx_error_underflow,
output wire logic stat_tx_byte,
output wire logic [15:0] stat_tx_pkt_len,
output wire logic stat_tx_pkt_ucast,
output wire logic stat_tx_pkt_mcast,
output wire logic stat_tx_pkt_bcast,
output wire logic stat_tx_pkt_vlan,
output wire logic stat_tx_pkt_good,
output wire logic stat_tx_pkt_bad,
output wire logic stat_tx_err_oversize,
output wire logic stat_tx_err_user,
output wire logic stat_tx_err_underflow,
output wire logic rx_start_packet,
output wire logic rx_error_bad_frame,
output wire logic rx_error_bad_fcs,
output wire logic stat_rx_byte,
output wire logic [15:0] stat_rx_pkt_len,
output wire logic stat_rx_pkt_fragment,
output wire logic stat_rx_pkt_jabber,
output wire logic stat_rx_pkt_ucast,
output wire logic stat_rx_pkt_mcast,
output wire logic stat_rx_pkt_bcast,
output wire logic stat_rx_pkt_vlan,
output wire logic stat_rx_pkt_good,
output wire logic stat_rx_pkt_bad,
output wire logic stat_rx_err_oversize,
output wire logic stat_rx_err_bad_fcs,
output wire logic stat_rx_err_bad_block,
output wire logic stat_rx_err_framing,
output wire logic stat_rx_err_preamble,
input wire logic stat_rx_fifo_drop = 1'b0,
output wire logic stat_tx_mcf,
output wire logic stat_rx_mcf,
output wire logic stat_tx_lfc_pkt,
@@ -118,8 +154,10 @@ module taxi_eth_mac_mii #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1,
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
@@ -205,7 +243,12 @@ taxi_eth_mac_1g #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
@@ -273,14 +316,45 @@ eth_mac_1g_inst (
.rx_mii_select(1'b1),
.tx_mii_select(1'b1),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
@@ -303,8 +377,10 @@ eth_mac_1g_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

69
rtl/eth/taxi_eth_mac_mii_fifo.sv
View File

@@ -22,6 +22,11 @@ module taxi_eth_mac_mii_fifo #
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -64,6 +69,13 @@ module taxi_eth_mac_mii_fifo #
output wire mii_tx_en,
output wire mii_tx_er,
/*
* Statistics
*/
input wire logic stat_clk,
input wire logic stat_rst,
taxi_axis_if.src m_axis_stat,
/*
* Status
*/
@@ -80,8 +92,10 @@ module taxi_eth_mac_mii_fifo #
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
input wire logic cfg_rx_enable = 1'b1
);
@@ -162,6 +176,8 @@ always_ff @(posedge logic_clk or posedge logic_rst) begin
end
end
wire stat_rx_fifo_drop;
taxi_eth_mac_mii #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -170,7 +186,12 @@ taxi_eth_mac_mii #(
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(1'b0),
.PFC_EN(1'b0),
.PAUSE_EN(1'b0)
.PAUSE_EN(1'b0),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
eth_mac_mii_inst (
.rst(rst),
@@ -233,14 +254,46 @@ eth_mac_mii_inst (
.tx_pause_req(0),
.tx_pause_ack(),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
// .rx_error_bad_frame(rx_error_bad_frame_int),
.tx_start_packet(),
.tx_error_underflow(tx_error_underflow_int),
.stat_tx_byte(),
.stat_tx_pkt_len(),
.stat_tx_pkt_ucast(),
.stat_tx_pkt_mcast(),
.stat_tx_pkt_bcast(),
.stat_tx_pkt_vlan(),
.stat_tx_pkt_good(),
.stat_tx_pkt_bad(),
.stat_tx_err_oversize(),
.stat_tx_err_user(),
.stat_tx_err_underflow(tx_error_underflow_int),
.rx_start_packet(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_byte(),
.stat_rx_pkt_len(),
.stat_rx_pkt_fragment(),
.stat_rx_pkt_jabber(),
.stat_rx_pkt_ucast(),
.stat_rx_pkt_mcast(),
.stat_rx_pkt_bcast(),
.stat_rx_pkt_vlan(),
.stat_rx_pkt_good(),
.stat_rx_pkt_bad(),
.stat_rx_err_oversize(),
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -263,8 +316,10 @@ eth_mac_mii_inst (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
@@ -427,7 +482,7 @@ rx_fifo (
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_overflow(stat_rx_fifo_drop),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),

5
tb/eth/taxi_eth_mac_1g/Makefile
View File

@@ -36,6 +36,11 @@ export PARAM_PTP_TS_W := 96
export PARAM_TX_TAG_W := 16
export PARAM_PFC_EN := 1
export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
ifeq ($(SIM), icarus)
PLUSARGS += -fst

144
tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py
View File

@@ -43,6 +43,7 @@ class TB:
cocotb.start_soon(Clock(dut.rx_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.tx_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.gmii_source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv,
dut.rx_clk, dut.rx_rst, dut.rx_clk_enable, dut.rx_mii_select)
@@ -53,6 +54,8 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
@@ -74,8 +77,12 @@ class TB:
dut.rx_mii_select.setimmediatevalue(0)
dut.tx_mii_select.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.stat_rx_fifo_drop.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
@@ -112,14 +119,17 @@ class TB:
async def reset(self):
self.dut.rx_rst.setimmediatevalue(0)
self.dut.tx_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@@ -165,7 +175,9 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -212,8 +224,10 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -256,8 +270,10 @@ async def run_test_tx_underrun(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -310,8 +326,10 @@ async def run_test_tx_error(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -345,13 +363,100 @@ async def run_test_tx_error(dut, ifg=12, enable_gen=None, mii_sel=False):
await RisingEdge(dut.tx_clk)
async def run_test_rx_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_tx_max_pkt_len.value = 1518
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 1518
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator_rx(enable_gen())
tb.set_enable_generator_tx(enable_gen())
await tb.reset()
test_data = bytes(x for x in range(60))
for k in range(3):
test_frame = GmiiFrame.from_payload(test_data)
if k == 1:
test_frame = GmiiFrame.from_payload(bytes(x % 256 for x in range(1515)))
await tb.gmii_source.send(test_frame)
for k in range(3):
rx_frame = await tb.axis_sink.recv()
if k == 1:
frame_error = rx_frame.tuser[-1] & 1
assert frame_error
else:
frame_error = rx_frame.tuser & 1
assert rx_frame.tdata == test_data
assert frame_error == 0
assert tb.axis_sink.empty()
await RisingEdge(dut.rx_clk)
await RisingEdge(dut.rx_clk)
async def run_test_tx_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_tx_max_pkt_len.value = 1518
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 1518
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
if enable_gen is not None:
tb.set_enable_generator_rx(enable_gen())
tb.set_enable_generator_tx(enable_gen())
await tb.reset()
test_data = bytes(x for x in range(60))
for k in range(3):
test_frame = AxiStreamFrame(test_data)
if k == 1:
test_frame = AxiStreamFrame(bytes(x % 256 for x in range(1515)))
await tb.axis_source.send(test_frame)
for k in range(3):
rx_frame = await tb.gmii_sink.recv()
if k == 1:
assert rx_frame.error[-1] == 1
else:
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.error is None
assert tb.gmii_sink.empty()
await RisingEdge(dut.tx_clk)
await RisingEdge(dut.tx_clk)
async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -501,8 +606,10 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True):
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -649,7 +756,10 @@ def cycle_en():
if cocotb.SIM_NAME:
for test in [run_test_rx, run_test_tx]:
for test in [
run_test_rx,
run_test_tx,
]:
factory = TestFactory(test)
factory.add_option("payload_lengths", [size_list])
@@ -659,7 +769,12 @@ if cocotb.SIM_NAME:
factory.add_option("mii_sel", [False, True])
factory.generate_tests()
for test in [run_test_tx_underrun, run_test_tx_error]:
for test in [
run_test_tx_underrun,
run_test_tx_error,
run_test_rx_oversize,
run_test_tx_oversize,
]:
factory = TestFactory(test)
factory.add_option("ifg", [12])
@@ -668,7 +783,11 @@ if cocotb.SIM_NAME:
factory.generate_tests()
if cocotb.top.PFC_EN.value:
for test in [run_test_lfc, run_test_pfc]:
for test in [
run_test_lfc,
run_test_pfc,
]:
factory = TestFactory(test)
factory.add_option("ifg", [12])
factory.add_option("enable_gen", [None, cycle_en])
@@ -718,6 +837,11 @@ def test_taxi_eth_mac_1g(request, pfc_en):
parameters['TX_TAG_W'] = 16
parameters['PFC_EN'] = pfc_en
parameters['PAUSE_EN'] = parameters['PFC_EN']
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

93
tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv
View File

@@ -25,7 +25,12 @@ module test_taxi_eth_mac_1g #
parameter PTP_TS_W = 96,
parameter TX_TAG_W = 16,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
/* verilator lint_on WIDTHTRUNC */
)
();
@@ -73,11 +78,39 @@ logic tx_clk_enable;
logic rx_mii_select;
logic tx_mii_select;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_start_packet;
logic tx_error_underflow;
logic stat_tx_byte;
logic [15:0] stat_tx_pkt_len;
logic stat_tx_pkt_ucast;
logic stat_tx_pkt_mcast;
logic stat_tx_pkt_bcast;
logic stat_tx_pkt_vlan;
logic stat_tx_pkt_good;
logic stat_tx_pkt_bad;
logic stat_tx_err_oversize;
logic stat_tx_err_user;
logic stat_tx_err_underflow;
logic rx_start_packet;
logic rx_error_bad_frame;
logic rx_error_bad_fcs;
logic stat_rx_byte;
logic [15:0] stat_rx_pkt_len;
logic stat_rx_pkt_fragment;
logic stat_rx_pkt_jabber;
logic stat_rx_pkt_ucast;
logic stat_rx_pkt_mcast;
logic stat_rx_pkt_bcast;
logic stat_rx_pkt_vlan;
logic stat_rx_pkt_good;
logic stat_rx_pkt_bad;
logic stat_rx_err_oversize;
logic stat_rx_err_bad_fcs;
logic stat_rx_err_bad_block;
logic stat_rx_err_framing;
logic stat_rx_err_preamble;
logic stat_rx_fifo_drop;
logic stat_tx_mcf;
logic stat_rx_mcf;
logic stat_tx_lfc_pkt;
@@ -97,8 +130,10 @@ logic [7:0] stat_rx_pfc_xon;
logic [7:0] stat_rx_pfc_xoff;
logic [7:0] stat_rx_pfc_paused;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
logic [47:0] cfg_mcf_rx_eth_dst_mcast;
logic cfg_mcf_rx_check_eth_dst_mcast;
@@ -139,7 +174,12 @@ taxi_eth_mac_1g #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
uut (
.rx_clk(rx_clk),
@@ -207,14 +247,45 @@ uut (
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
@@ -237,8 +308,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

5
tb/eth/taxi_eth_mac_1g_fifo/Makefile
View File

@@ -33,6 +33,11 @@ export PARAM_AXIS_DATA_W := 8
export PARAM_PADDING_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_TX_TAG_W := 16
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1

24
tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py
View File

@@ -39,6 +39,7 @@ class TB:
cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.rx_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.tx_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.gmii_source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv,
dut.rx_clk, dut.rx_rst, dut.rx_clk_enable, dut.rx_mii_select)
@@ -49,11 +50,18 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.rx_clk_enable.setimmediatevalue(1)
dut.tx_clk_enable.setimmediatevalue(1)
dut.rx_mii_select.setimmediatevalue(0)
dut.tx_mii_select.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
@@ -61,16 +69,19 @@ class TB:
self.dut.logic_rst.setimmediatevalue(0)
self.dut.rx_rst.setimmediatevalue(0)
self.dut.tx_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
self.dut.stat_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
self.dut.stat_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.logic_clk)
@@ -116,7 +127,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -150,7 +162,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb = TB(dut)
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@@ -242,6 +255,11 @@ def test_taxi_eth_mac_1g_fifo(request):
parameters['PADDING_EN'] = 1
parameters['MIN_FRAME_LEN'] = 64
parameters['TX_TAG_W'] = 16
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1

29
tb/eth/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv
View File

@@ -23,6 +23,11 @@ module test_taxi_eth_mac_1g_fifo #
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_TAG_W = 16,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -66,6 +71,10 @@ logic tx_clk_enable;
logic rx_mii_select;
logic tx_mii_select;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
@@ -76,14 +85,21 @@ logic rx_fifo_overflow;
logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
taxi_eth_mac_1g_fifo #(
.DATA_W(DATA_W),
.PADDING_EN(PADDING_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
@@ -135,6 +151,13 @@ uut (
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
@@ -151,8 +174,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable)
);

5
tb/eth/taxi_eth_mac_1g_gmii/Makefile
View File

@@ -38,6 +38,11 @@ export PARAM_PTP_TS_W := 96
export PARAM_TX_TAG_W := 16
export PARAM_PFC_EN := 1
export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
ifeq ($(SIM), icarus)
PLUSARGS += -fst

41
tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py
View File

@@ -37,6 +37,7 @@ class TB:
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.gtx_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.gmii_phy = GmiiPhy(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.mii_tx_clk, dut.gmii_tx_clk,
dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv, dut.gmii_rx_clk, speed=speed)
@@ -50,6 +51,8 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.mii_tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.gmii_rx_clk, dut.rx_rst)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
@@ -66,8 +69,12 @@ class TB:
dut.tx_lfc_pause_en.setimmediatevalue(0)
dut.tx_pause_req.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.stat_rx_fifo_drop.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
@@ -103,12 +110,15 @@ class TB:
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.gtx_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.gtx_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@@ -118,7 +128,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -174,7 +185,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -227,7 +239,8 @@ async def run_test_tx_underrun(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -272,7 +285,8 @@ async def run_test_tx_error(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -309,9 +323,11 @@ async def run_test_lfc(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -457,9 +473,11 @@ async def run_test_pfc(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -670,6 +688,11 @@ def test_taxi_eth_mac_1g_gmii(request, pfc_en):
parameters['TX_TAG_W'] = 16
parameters['PFC_EN'] = pfc_en
parameters['PAUSE_EN'] = parameters['PFC_EN']
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

93
tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
View File

@@ -27,7 +27,12 @@ module test_taxi_eth_mac_1g_gmii #
parameter PTP_TS_W = 96,
parameter TX_TAG_W = 16,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
/* verilator lint_on WIDTHTRUNC */
)
();
@@ -76,11 +81,39 @@ logic tx_lfc_pause_en;
logic tx_pause_req;
logic tx_pause_ack;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_start_packet;
logic tx_error_underflow;
logic stat_tx_byte;
logic [15:0] stat_tx_pkt_len;
logic stat_tx_pkt_ucast;
logic stat_tx_pkt_mcast;
logic stat_tx_pkt_bcast;
logic stat_tx_pkt_vlan;
logic stat_tx_pkt_good;
logic stat_tx_pkt_bad;
logic stat_tx_err_oversize;
logic stat_tx_err_user;
logic stat_tx_err_underflow;
logic rx_start_packet;
logic rx_error_bad_frame;
logic rx_error_bad_fcs;
logic stat_rx_byte;
logic [15:0] stat_rx_pkt_len;
logic stat_rx_pkt_fragment;
logic stat_rx_pkt_jabber;
logic stat_rx_pkt_ucast;
logic stat_rx_pkt_mcast;
logic stat_rx_pkt_bcast;
logic stat_rx_pkt_vlan;
logic stat_rx_pkt_good;
logic stat_rx_pkt_bad;
logic stat_rx_err_oversize;
logic stat_rx_err_bad_fcs;
logic stat_rx_err_bad_block;
logic stat_rx_err_framing;
logic stat_rx_err_preamble;
logic stat_rx_fifo_drop;
logic [1:0] link_speed;
logic stat_tx_mcf;
logic stat_rx_mcf;
@@ -101,8 +134,10 @@ logic [7:0] stat_rx_pfc_xon;
logic [7:0] stat_rx_pfc_xoff;
logic [7:0] stat_rx_pfc_paused;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
logic [47:0] cfg_mcf_rx_eth_dst_mcast;
logic cfg_mcf_rx_check_eth_dst_mcast;
@@ -145,7 +180,12 @@ taxi_eth_mac_1g_gmii #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
uut (
.gtx_clk(gtx_clk),
@@ -210,14 +250,45 @@ uut (
.tx_pause_req(tx_pause_req),
.tx_pause_ack(tx_pause_ack),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.link_speed(link_speed),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
@@ -241,8 +312,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

5
tb/eth/taxi_eth_mac_1g_gmii_fifo/Makefile
View File

@@ -35,6 +35,11 @@ export PARAM_AXIS_DATA_W := 8
export PARAM_PADDING_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_TX_TAG_W := 16
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1

21
tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py
View File

@@ -33,6 +33,7 @@ class TB:
cocotb.start_soon(Clock(dut.gtx_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.gmii_phy = GmiiPhy(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.mii_tx_clk, dut.gmii_tx_clk,
dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv, dut.gmii_rx_clk, speed=speed)
@@ -41,21 +42,28 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
self.dut.logic_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 1
self.dut.logic_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 0
self.dut.logic_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
@@ -65,7 +73,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -103,7 +112,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -200,6 +210,11 @@ def test_taxi_eth_mac_1g_gmii_fifo(request):
parameters['PADDING_EN'] = 1
parameters['MIN_FRAME_LEN'] = 64
parameters['TX_TAG_W'] = 16
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1

29
tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
View File

@@ -25,6 +25,11 @@ module test_taxi_eth_mac_1g_gmii_fifo #
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_TAG_W = 16,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -65,6 +70,10 @@ logic [7:0] gmii_txd;
logic gmii_tx_en;
logic gmii_tx_er;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
@@ -76,8 +85,10 @@ logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [1:0] link_speed;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
taxi_eth_mac_1g_gmii_fifo #(
@@ -86,6 +97,11 @@ taxi_eth_mac_1g_gmii_fifo #(
.FAMILY(FAMILY),
.PADDING_EN(PADDING_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
@@ -130,6 +146,13 @@ uut (
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
@@ -147,8 +170,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable)
);

5
tb/eth/taxi_eth_mac_1g_rgmii/Makefile
View File

@@ -39,6 +39,11 @@ export PARAM_PTP_TS_W := 96
export PARAM_TX_TAG_W := 16
export PARAM_PFC_EN := 1
export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
ifeq ($(SIM), icarus)
PLUSARGS += -fst

43
tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py
View File

@@ -20,6 +20,7 @@ import pytest
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.utils import get_time_from_sim_steps
from cocotb.regression import TestFactory
@@ -35,6 +36,8 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.rgmii_phy = RgmiiPhy(dut.rgmii_txd, dut.rgmii_tx_ctl, dut.rgmii_tx_clk,
dut.rgmii_rxd, dut.rgmii_rx_ctl, dut.rgmii_rx_clk, speed=speed)
@@ -43,6 +46,8 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.gtx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
@@ -59,8 +64,12 @@ class TB:
dut.tx_lfc_pause_en.setimmediatevalue(0)
dut.tx_pause_req.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.stat_rx_fifo_drop.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
@@ -101,12 +110,15 @@ class TB:
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
@@ -128,7 +140,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -184,7 +197,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -222,7 +236,8 @@ async def run_test_tx_underrun(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -273,7 +288,8 @@ async def run_test_tx_error(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -310,9 +326,11 @@ async def run_test_lfc(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -458,9 +476,11 @@ async def run_test_pfc(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -673,6 +693,11 @@ def test_taxi_eth_mac_1g_rgmii(request, pfc_en):
parameters['TX_TAG_W'] = 16
parameters['PFC_EN'] = pfc_en
parameters['PAUSE_EN'] = parameters['PFC_EN']
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

93
tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
View File

@@ -28,7 +28,12 @@ module test_taxi_eth_mac_1g_rgmii #
parameter PTP_TS_W = 96,
parameter TX_TAG_W = 16,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
/* verilator lint_on WIDTHTRUNC */
)
();
@@ -75,11 +80,39 @@ logic tx_lfc_pause_en;
logic tx_pause_req;
logic tx_pause_ack;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_start_packet;
logic tx_error_underflow;
logic stat_tx_byte;
logic [15:0] stat_tx_pkt_len;
logic stat_tx_pkt_ucast;
logic stat_tx_pkt_mcast;
logic stat_tx_pkt_bcast;
logic stat_tx_pkt_vlan;
logic stat_tx_pkt_good;
logic stat_tx_pkt_bad;
logic stat_tx_err_oversize;
logic stat_tx_err_user;
logic stat_tx_err_underflow;
logic rx_start_packet;
logic rx_error_bad_frame;
logic rx_error_bad_fcs;
logic stat_rx_byte;
logic [15:0] stat_rx_pkt_len;
logic stat_rx_pkt_fragment;
logic stat_rx_pkt_jabber;
logic stat_rx_pkt_ucast;
logic stat_rx_pkt_mcast;
logic stat_rx_pkt_bcast;
logic stat_rx_pkt_vlan;
logic stat_rx_pkt_good;
logic stat_rx_pkt_bad;
logic stat_rx_err_oversize;
logic stat_rx_err_bad_fcs;
logic stat_rx_err_bad_block;
logic stat_rx_err_framing;
logic stat_rx_err_preamble;
logic stat_rx_fifo_drop;
logic [1:0] link_speed;
logic stat_tx_mcf;
logic stat_rx_mcf;
@@ -100,8 +133,10 @@ logic [7:0] stat_rx_pfc_xon;
logic [7:0] stat_rx_pfc_xoff;
logic [7:0] stat_rx_pfc_paused;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
logic [47:0] cfg_mcf_rx_eth_dst_mcast;
logic cfg_mcf_rx_check_eth_dst_mcast;
@@ -145,7 +180,12 @@ taxi_eth_mac_1g_rgmii #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
uut (
.gtx_clk(gtx_clk),
@@ -208,14 +248,45 @@ uut (
.tx_pause_req(tx_pause_req),
.tx_pause_ack(tx_pause_ack),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.link_speed(link_speed),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
@@ -239,8 +310,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

5
tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile
View File

@@ -36,6 +36,11 @@ export PARAM_AXIS_DATA_W := 8
export PARAM_PADDING_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_TX_TAG_W := 16
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1

21
tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py
View File

@@ -32,6 +32,7 @@ class TB:
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.rgmii_phy = RgmiiPhy(dut.rgmii_txd, dut.rgmii_tx_ctl, dut.rgmii_tx_clk,
dut.rgmii_rxd, dut.rgmii_rx_ctl, dut.rgmii_rx_clk, speed=speed)
@@ -40,8 +41,12 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.gtx_clk.setimmediatevalue(0)
@@ -52,14 +57,17 @@ class TB:
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
self.dut.logic_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 1
self.dut.logic_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 0
self.dut.logic_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
@@ -81,7 +89,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -119,7 +128,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -217,6 +227,11 @@ def test_taxi_eth_mac_1g_rgmii_fifo(request):
parameters['PADDING_EN'] = 1
parameters['MIN_FRAME_LEN'] = 64
parameters['TX_TAG_W'] = 16
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1

29
tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
View File

@@ -26,6 +26,11 @@ module test_taxi_eth_mac_1g_rgmii_fifo #
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_TAG_W = 16,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -64,6 +69,10 @@ logic rgmii_tx_clk;
logic [3:0] rgmii_txd;
logic rgmii_tx_ctl;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
@@ -75,8 +84,10 @@ logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [1:0] link_speed;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
taxi_eth_mac_1g_rgmii_fifo #(
@@ -86,6 +97,11 @@ taxi_eth_mac_1g_rgmii_fifo #(
.USE_CLK90(USE_CLK90),
.PADDING_EN(PADDING_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
@@ -128,6 +144,13 @@ uut (
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
@@ -145,8 +168,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable)
);

5
tb/eth/taxi_eth_mac_mii/Makefile
View File

@@ -38,6 +38,11 @@ export PARAM_PTP_TS_W := 96
export PARAM_TX_TAG_W := 16
export PARAM_PFC_EN := 1
export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
ifeq ($(SIM), icarus)
PLUSARGS += -fst

43
tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py
View File

@@ -20,6 +20,7 @@ import pytest
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.utils import get_time_from_sim_steps
from cocotb.regression import TestFactory
@@ -35,6 +36,8 @@ class TB:
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.mii_phy = MiiPhy(dut.mii_txd, dut.mii_tx_er, dut.mii_tx_en, dut.mii_tx_clk,
dut.mii_rxd, dut.mii_rx_er, dut.mii_rx_dv, dut.mii_rx_clk, speed=speed)
@@ -43,6 +46,8 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.mii_tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.mii_rx_clk, dut.rx_rst)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
@@ -59,8 +64,12 @@ class TB:
dut.tx_lfc_pause_en.setimmediatevalue(0)
dut.tx_pause_req.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.stat_rx_fifo_drop.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
@@ -96,12 +105,15 @@ class TB:
async def reset(self):
self.dut.rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
self.dut.rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.tx_clk)
await RisingEdge(self.dut.tx_clk)
@@ -111,7 +123,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -158,7 +171,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -189,7 +203,8 @@ async def run_test_tx_underrun(dut, ifg=12):
tb = TB(dut)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -234,7 +249,8 @@ async def run_test_tx_error(dut, ifg=12):
tb = TB(dut)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -271,9 +287,11 @@ async def run_test_lfc(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -419,9 +437,11 @@ async def run_test_pfc(dut, ifg=12, speed=1000e6):
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -631,6 +651,11 @@ def test_taxi_eth_mac_mii(request, pfc_en):
parameters['TX_TAG_W'] = 16
parameters['PFC_EN'] = pfc_en
parameters['PAUSE_EN'] = parameters['PFC_EN']
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

93
tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
View File

@@ -27,7 +27,12 @@ module test_taxi_eth_mac_mii #
parameter PTP_TS_W = 96,
parameter TX_TAG_W = 16,
parameter logic PFC_EN = 1'b0,
parameter logic PAUSE_EN = PFC_EN
parameter logic PAUSE_EN = PFC_EN,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024
/* verilator lint_on WIDTHTRUNC */
)
();
@@ -74,11 +79,39 @@ logic tx_lfc_pause_en;
logic tx_pause_req;
logic tx_pause_ack;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_start_packet;
logic tx_error_underflow;
logic stat_tx_byte;
logic [15:0] stat_tx_pkt_len;
logic stat_tx_pkt_ucast;
logic stat_tx_pkt_mcast;
logic stat_tx_pkt_bcast;
logic stat_tx_pkt_vlan;
logic stat_tx_pkt_good;
logic stat_tx_pkt_bad;
logic stat_tx_err_oversize;
logic stat_tx_err_user;
logic stat_tx_err_underflow;
logic rx_start_packet;
logic rx_error_bad_frame;
logic rx_error_bad_fcs;
logic stat_rx_byte;
logic [15:0] stat_rx_pkt_len;
logic stat_rx_pkt_fragment;
logic stat_rx_pkt_jabber;
logic stat_rx_pkt_ucast;
logic stat_rx_pkt_mcast;
logic stat_rx_pkt_bcast;
logic stat_rx_pkt_vlan;
logic stat_rx_pkt_good;
logic stat_rx_pkt_bad;
logic stat_rx_err_oversize;
logic stat_rx_err_bad_fcs;
logic stat_rx_err_bad_block;
logic stat_rx_err_framing;
logic stat_rx_err_preamble;
logic stat_rx_fifo_drop;
logic stat_tx_mcf;
logic stat_rx_mcf;
logic stat_tx_lfc_pkt;
@@ -98,8 +131,10 @@ logic [7:0] stat_rx_pfc_xon;
logic [7:0] stat_rx_pfc_xoff;
logic [7:0] stat_rx_pfc_paused;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
logic [47:0] cfg_mcf_rx_eth_dst_mcast;
logic cfg_mcf_rx_check_eth_dst_mcast;
@@ -142,7 +177,12 @@ taxi_eth_mac_mii #(
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(PFC_EN),
.PAUSE_EN(PAUSE_EN)
.PAUSE_EN(PAUSE_EN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
)
uut (
.rst(rst),
@@ -205,14 +245,45 @@ uut (
.tx_pause_req(tx_pause_req),
.tx_pause_ack(tx_pause_ack),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.stat_rx_byte(stat_rx_byte),
.stat_rx_pkt_len(stat_rx_pkt_len),
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
.stat_rx_pkt_good(stat_rx_pkt_good),
.stat_rx_pkt_bad(stat_rx_pkt_bad),
.stat_rx_err_oversize(stat_rx_err_oversize),
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
.stat_rx_err_bad_block(stat_rx_err_bad_block),
.stat_rx_err_framing(stat_rx_err_framing),
.stat_rx_err_preamble(stat_rx_err_preamble),
.stat_rx_fifo_drop(stat_rx_fifo_drop),
.stat_tx_mcf(stat_tx_mcf),
.stat_rx_mcf(stat_rx_mcf),
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
@@ -235,8 +306,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),

5
tb/eth/taxi_eth_mac_mii_fifo/Makefile
View File

@@ -35,6 +35,11 @@ export PARAM_AXIS_DATA_W := 8
export PARAM_PADDING_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_TX_TAG_W := 16
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1

21
tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py
View File

@@ -32,6 +32,7 @@ class TB:
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.logic_clk, 40, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.mii_phy = MiiPhy(dut.mii_txd, dut.mii_tx_er, dut.mii_tx_en, dut.mii_tx_clk,
dut.mii_rxd, dut.mii_rx_er, dut.mii_rx_dv, dut.mii_rx_clk, speed=speed)
@@ -40,18 +41,25 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 1
self.dut.stat_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 0
self.dut.stat_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.logic_clk)
@@ -61,7 +69,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -89,7 +98,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -176,6 +186,11 @@ def test_taxi_eth_mac_mii_fifo(request):
parameters['PADDING_EN'] = 1
parameters['MIN_FRAME_LEN'] = 64
parameters['TX_TAG_W'] = 16
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1

29
tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
View File

@@ -25,6 +25,11 @@ module test_taxi_eth_mac_mii_fifo #
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_TAG_W = 16,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -62,6 +67,10 @@ logic [3:0] mii_txd;
logic mii_tx_en;
logic mii_tx_er;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
@@ -72,8 +81,10 @@ logic rx_fifo_overflow;
logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
taxi_eth_mac_mii_fifo #(
@@ -82,6 +93,11 @@ taxi_eth_mac_mii_fifo #(
.FAMILY(FAMILY),
.PADDING_EN(PADDING_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
@@ -124,6 +140,13 @@ uut (
.mii_tx_en(mii_tx_en),
.mii_tx_er(mii_tx_er),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
@@ -140,8 +163,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable)
);