mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 00:48:40 -08:00
eth: Add MAC statistics module to 1G MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -1,6 +1,7 @@
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taxi_eth_mac_1g.sv
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taxi_axis_gmii_rx.sv
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taxi_axis_gmii_tx.sv
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taxi_eth_mac_stats.f
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taxi_mac_ctrl_tx.sv
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taxi_mac_ctrl_rx.sv
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taxi_mac_pause_ctrl_tx.sv
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@@ -23,7 +23,12 @@ module taxi_eth_mac_1g #
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parameter logic PTP_TS_EN = 1'b0,
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parameter PTP_TS_W = 96,
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parameter logic PFC_EN = 1'b0,
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parameter logic PAUSE_EN = PFC_EN
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parameter logic PAUSE_EN = PFC_EN,
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parameter logic STAT_EN = 1'b0,
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024
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)
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(
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input wire logic rx_clk,
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@@ -91,14 +96,45 @@ module taxi_eth_mac_1g #
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input wire logic rx_mii_select = 1'b0,
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input wire logic tx_mii_select = 1'b0,
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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output wire logic tx_start_packet,
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output wire logic tx_error_underflow,
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output wire logic stat_tx_byte,
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output wire logic [15:0] stat_tx_pkt_len,
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output wire logic stat_tx_pkt_ucast,
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output wire logic stat_tx_pkt_mcast,
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output wire logic stat_tx_pkt_bcast,
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output wire logic stat_tx_pkt_vlan,
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output wire logic stat_tx_pkt_good,
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output wire logic stat_tx_pkt_bad,
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output wire logic stat_tx_err_oversize,
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output wire logic stat_tx_err_user,
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output wire logic stat_tx_err_underflow,
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output wire logic rx_start_packet,
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output wire logic rx_error_bad_frame,
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output wire logic rx_error_bad_fcs,
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output wire logic stat_rx_byte,
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output wire logic [15:0] stat_rx_pkt_len,
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output wire logic stat_rx_pkt_fragment,
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output wire logic stat_rx_pkt_jabber,
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output wire logic stat_rx_pkt_ucast,
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output wire logic stat_rx_pkt_mcast,
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output wire logic stat_rx_pkt_bcast,
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output wire logic stat_rx_pkt_vlan,
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output wire logic stat_rx_pkt_good,
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output wire logic stat_rx_pkt_bad,
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output wire logic stat_rx_err_oversize,
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output wire logic stat_rx_err_bad_fcs,
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output wire logic stat_rx_err_bad_block,
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output wire logic stat_rx_err_framing,
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output wire logic stat_rx_err_preamble,
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input wire logic stat_rx_fifo_drop = 1'b0,
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output wire logic stat_tx_mcf,
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output wire logic stat_rx_mcf,
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output wire logic stat_tx_lfc_pkt,
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@@ -121,8 +157,10 @@ module taxi_eth_mac_1g #
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/*
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* Configuration
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*/
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input wire logic [7:0] cfg_ifg = 8'd12,
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input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
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input wire logic [7:0] cfg_tx_ifg = 8'd12,
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input wire logic cfg_tx_enable = 1'b1,
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input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
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input wire logic cfg_rx_enable = 1'b1,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
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input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
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@@ -202,28 +240,28 @@ axis_gmii_rx_inst (
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/*
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* Configuration
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*/
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.cfg_rx_max_pkt_len(16'd9218),
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.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
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.cfg_rx_enable(cfg_rx_enable),
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/*
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* Status
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*/
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.rx_start_packet(rx_start_packet),
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.stat_rx_byte(),
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.stat_rx_pkt_len(),
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.stat_rx_pkt_fragment(),
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.stat_rx_pkt_jabber(),
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.stat_rx_pkt_ucast(),
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.stat_rx_pkt_mcast(),
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.stat_rx_pkt_bcast(),
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.stat_rx_pkt_vlan(),
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.stat_rx_pkt_good(),
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.stat_rx_pkt_bad(rx_error_bad_frame),
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.stat_rx_err_oversize(),
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.stat_rx_err_bad_fcs(rx_error_bad_fcs),
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.stat_rx_err_bad_block(),
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.stat_rx_err_framing(),
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.stat_rx_err_preamble()
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.stat_rx_byte(stat_rx_byte),
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.stat_rx_pkt_len(stat_rx_pkt_len),
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.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
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.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
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.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
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.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
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.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
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.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
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.stat_rx_pkt_good(stat_rx_pkt_good),
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.stat_rx_pkt_bad(stat_rx_pkt_bad),
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.stat_rx_err_oversize(stat_rx_err_oversize),
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.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
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.stat_rx_err_bad_block(stat_rx_err_bad_block),
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.stat_rx_err_framing(stat_rx_err_framing),
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.stat_rx_err_preamble(stat_rx_err_preamble)
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);
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taxi_axis_gmii_tx #(
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@@ -265,28 +303,112 @@ axis_gmii_tx_inst (
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/*
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* Configuration
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*/
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.cfg_tx_max_pkt_len(16'd9218),
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.cfg_tx_ifg(cfg_ifg),
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.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
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.cfg_tx_ifg(cfg_tx_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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/*
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* Status
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*/
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.tx_start_packet(tx_start_packet),
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.stat_tx_byte(),
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.stat_tx_pkt_len(),
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.stat_tx_pkt_ucast(),
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.stat_tx_pkt_mcast(),
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.stat_tx_pkt_bcast(),
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.stat_tx_pkt_vlan(),
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.stat_tx_pkt_good(),
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.stat_tx_pkt_bad(),
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.stat_tx_err_oversize(),
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.stat_tx_err_user(),
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.stat_tx_err_underflow(tx_error_underflow)
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.stat_tx_byte(stat_tx_byte),
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.stat_tx_pkt_len(stat_tx_pkt_len),
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.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
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.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
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.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
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.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
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.stat_tx_pkt_good(stat_tx_pkt_good),
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.stat_tx_pkt_bad(stat_tx_pkt_bad),
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.stat_tx_err_oversize(stat_tx_err_oversize),
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.stat_tx_err_user(stat_tx_err_user),
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.stat_tx_err_underflow(stat_tx_err_underflow)
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);
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generate
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if (STAT_EN) begin : stats
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taxi_eth_mac_stats #(
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.STAT_TX_LEVEL(STAT_TX_LEVEL),
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.STAT_RX_LEVEL(STAT_RX_LEVEL),
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.STAT_ID_BASE(STAT_ID_BASE),
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.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
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.INC_W(1)
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)
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mac_stats_inst (
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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/*
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* Statistics
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*/
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.stat_clk(stat_clk),
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.stat_rst(stat_rst),
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.m_axis_stat(m_axis_stat),
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/*
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* Status
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*/
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.tx_start_packet(tx_start_packet),
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.stat_tx_byte(stat_tx_byte),
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.stat_tx_pkt_len(stat_tx_pkt_len),
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.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
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.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
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.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
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.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
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.stat_tx_pkt_good(stat_tx_pkt_good),
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.stat_tx_pkt_bad(stat_tx_pkt_bad),
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.stat_tx_err_oversize(stat_tx_err_oversize),
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.stat_tx_err_user(stat_tx_err_user),
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.stat_tx_err_underflow(stat_tx_err_underflow),
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.rx_start_packet(rx_start_packet),
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.stat_rx_byte(stat_rx_byte),
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.stat_rx_pkt_len(stat_rx_pkt_len),
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.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
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.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
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.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
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.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
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.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
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.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
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.stat_rx_pkt_good(stat_rx_pkt_good),
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.stat_rx_pkt_bad(stat_rx_pkt_bad),
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.stat_rx_err_oversize(stat_rx_err_oversize),
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.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
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.stat_rx_err_bad_block(stat_rx_err_bad_block),
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.stat_rx_err_framing(stat_rx_err_framing),
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.stat_rx_err_preamble(stat_rx_err_preamble),
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.stat_rx_fifo_drop(stat_rx_fifo_drop),
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.stat_tx_mcf(stat_tx_mcf),
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.stat_rx_mcf(stat_rx_mcf),
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.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
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.stat_tx_lfc_xon(stat_tx_lfc_xon),
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.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
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.stat_tx_lfc_paused(stat_tx_lfc_paused),
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.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
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.stat_tx_pfc_xon(stat_tx_pfc_xon),
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.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
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.stat_tx_pfc_paused(stat_tx_pfc_paused),
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.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
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.stat_rx_lfc_xon(stat_rx_lfc_xon),
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.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
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.stat_rx_lfc_paused(stat_rx_lfc_paused),
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.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
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.stat_rx_pfc_xon(stat_rx_pfc_xon),
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.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
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.stat_rx_pfc_paused(stat_rx_pfc_paused)
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);
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end else begin
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assign m_axis_stat.tdata = '0;
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assign m_axis_stat.tkeep = '0;
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assign m_axis_stat.tlast = '0;
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assign m_axis_stat.tvalid = '0;
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assign m_axis_stat.tid = '0;
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assign m_axis_stat.tdest = '0;
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assign m_axis_stat.tuser = '0;
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end
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if (MAC_CTRL_EN) begin : mac_ctrl
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@@ -603,8 +725,6 @@ end else begin
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end
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endgenerate
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endmodule
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`resetall
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@@ -20,6 +20,11 @@ module taxi_eth_mac_1g_fifo #
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parameter DATA_W = 8,
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parameter logic PADDING_EN = 1'b1,
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parameter MIN_FRAME_LEN = 64,
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parameter logic STAT_EN = 1'b0,
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024,
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parameter TX_FIFO_DEPTH = 4096,
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parameter TX_FIFO_RAM_PIPELINE = 1,
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parameter logic TX_FRAME_FIFO = 1'b1,
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@@ -71,6 +76,13 @@ module taxi_eth_mac_1g_fifo #
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input wire logic rx_mii_select = 1'b0,
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input wire logic tx_mii_select = 1'b0,
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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@@ -87,8 +99,10 @@ module taxi_eth_mac_1g_fifo #
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/*
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* Configuration
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*/
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input wire logic [7:0] cfg_ifg = 8'd12,
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input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
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input wire logic [7:0] cfg_tx_ifg = 8'd12,
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input wire logic cfg_tx_enable = 1'b1,
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input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
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input wire logic cfg_rx_enable = 1'b1
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);
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@@ -164,13 +178,20 @@ always_ff @(posedge logic_clk or posedge logic_rst) begin
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end
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end
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wire stat_rx_fifo_drop;
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taxi_eth_mac_1g #(
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.DATA_W(DATA_W),
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.PADDING_EN(PADDING_EN),
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.MIN_FRAME_LEN(MIN_FRAME_LEN),
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.PTP_TS_EN(1'b0),
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.PFC_EN(1'b0),
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.PAUSE_EN(1'b0)
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.PAUSE_EN(1'b0),
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.STAT_EN(STAT_EN),
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.STAT_TX_LEVEL(STAT_TX_LEVEL),
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.STAT_RX_LEVEL(STAT_RX_LEVEL),
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.STAT_ID_BASE(STAT_ID_BASE),
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.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
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)
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eth_mac_1g_inst (
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.tx_clk(tx_clk),
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@@ -238,14 +259,46 @@ eth_mac_1g_inst (
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.rx_mii_select(rx_mii_select),
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.tx_mii_select(tx_mii_select),
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/*
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* Statistics
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*/
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.stat_clk(stat_clk),
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.stat_rst(stat_rst),
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.m_axis_stat(m_axis_stat),
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/*
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* Status
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*/
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// .rx_error_bad_frame(rx_error_bad_frame_int),
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.tx_start_packet(),
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.tx_error_underflow(tx_error_underflow_int),
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.stat_tx_byte(),
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.stat_tx_pkt_len(),
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.stat_tx_pkt_ucast(),
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.stat_tx_pkt_mcast(),
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.stat_tx_pkt_bcast(),
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.stat_tx_pkt_vlan(),
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.stat_tx_pkt_good(),
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.stat_tx_pkt_bad(),
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.stat_tx_err_oversize(),
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.stat_tx_err_user(),
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.stat_tx_err_underflow(tx_error_underflow_int),
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.rx_start_packet(),
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.rx_error_bad_frame(rx_error_bad_frame_int),
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.rx_error_bad_fcs(rx_error_bad_fcs_int),
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.stat_rx_byte(),
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.stat_rx_pkt_len(),
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.stat_rx_pkt_fragment(),
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.stat_rx_pkt_jabber(),
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.stat_rx_pkt_ucast(),
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.stat_rx_pkt_mcast(),
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.stat_rx_pkt_bcast(),
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.stat_rx_pkt_vlan(),
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.stat_rx_pkt_good(),
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.stat_rx_pkt_bad(),
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.stat_rx_err_oversize(),
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.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
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.stat_rx_err_bad_block(),
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.stat_rx_err_framing(),
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.stat_rx_err_preamble(),
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.stat_rx_fifo_drop(stat_rx_fifo_drop),
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.stat_tx_mcf(),
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.stat_rx_mcf(),
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.stat_tx_lfc_pkt(),
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@@ -268,8 +321,10 @@ eth_mac_1g_inst (
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/*
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* Configuration
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*/
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.cfg_ifg(cfg_ifg),
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.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
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.cfg_tx_ifg(cfg_tx_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
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.cfg_rx_enable(cfg_rx_enable),
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.cfg_mcf_rx_eth_dst_mcast('0),
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.cfg_mcf_rx_check_eth_dst_mcast('0),
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@@ -432,7 +487,7 @@ rx_fifo (
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_overflow(stat_rx_fifo_drop),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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@@ -25,7 +25,12 @@ module taxi_eth_mac_1g_gmii #
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parameter logic PTP_TS_EN = 1'b0,
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parameter PTP_TS_W = 96,
|
||||
parameter logic PFC_EN = 1'b0,
|
||||
parameter logic PAUSE_EN = PFC_EN
|
||||
parameter logic PAUSE_EN = PFC_EN,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024
|
||||
)
|
||||
(
|
||||
input wire logic gtx_clk,
|
||||
@@ -90,14 +95,45 @@ module taxi_eth_mac_1g_gmii #
|
||||
input wire logic tx_pause_req = 1'b0,
|
||||
output wire logic tx_pause_ack,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic tx_start_packet,
|
||||
output wire logic tx_error_underflow,
|
||||
output wire logic stat_tx_byte,
|
||||
output wire logic [15:0] stat_tx_pkt_len,
|
||||
output wire logic stat_tx_pkt_ucast,
|
||||
output wire logic stat_tx_pkt_mcast,
|
||||
output wire logic stat_tx_pkt_bcast,
|
||||
output wire logic stat_tx_pkt_vlan,
|
||||
output wire logic stat_tx_pkt_good,
|
||||
output wire logic stat_tx_pkt_bad,
|
||||
output wire logic stat_tx_err_oversize,
|
||||
output wire logic stat_tx_err_user,
|
||||
output wire logic stat_tx_err_underflow,
|
||||
output wire logic rx_start_packet,
|
||||
output wire logic rx_error_bad_frame,
|
||||
output wire logic rx_error_bad_fcs,
|
||||
output wire logic stat_rx_byte,
|
||||
output wire logic [15:0] stat_rx_pkt_len,
|
||||
output wire logic stat_rx_pkt_fragment,
|
||||
output wire logic stat_rx_pkt_jabber,
|
||||
output wire logic stat_rx_pkt_ucast,
|
||||
output wire logic stat_rx_pkt_mcast,
|
||||
output wire logic stat_rx_pkt_bcast,
|
||||
output wire logic stat_rx_pkt_vlan,
|
||||
output wire logic stat_rx_pkt_good,
|
||||
output wire logic stat_rx_pkt_bad,
|
||||
output wire logic stat_rx_err_oversize,
|
||||
output wire logic stat_rx_err_bad_fcs,
|
||||
output wire logic stat_rx_err_bad_block,
|
||||
output wire logic stat_rx_err_framing,
|
||||
output wire logic stat_rx_err_preamble,
|
||||
input wire logic stat_rx_fifo_drop = 1'b0,
|
||||
output wire logic [1:0] link_speed,
|
||||
output wire logic stat_tx_mcf,
|
||||
output wire logic stat_rx_mcf,
|
||||
@@ -121,8 +157,10 @@ module taxi_eth_mac_1g_gmii #
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [7:0] cfg_ifg = 8'd12,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
|
||||
input wire logic cfg_rx_enable = 1'b1,
|
||||
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
|
||||
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
|
||||
@@ -301,7 +339,12 @@ taxi_eth_mac_1g #(
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN)
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
|
||||
)
|
||||
eth_mac_1g_inst (
|
||||
.tx_clk(tx_clk),
|
||||
@@ -369,14 +412,45 @@ eth_mac_1g_inst (
|
||||
.rx_mii_select(rx_mii_select_sync),
|
||||
.tx_mii_select(tx_mii_select_sync),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.tx_error_underflow(tx_error_underflow),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_bad_frame(rx_error_bad_frame),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
@@ -399,8 +473,10 @@ eth_mac_1g_inst (
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(cfg_ifg),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
|
||||
@@ -22,6 +22,11 @@ module taxi_eth_mac_1g_gmii_fifo #
|
||||
parameter string FAMILY = "virtex7",
|
||||
parameter logic PADDING_EN = 1'b1,
|
||||
parameter MIN_FRAME_LEN = 64,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter TX_FIFO_DEPTH = 4096,
|
||||
parameter TX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic TX_FRAME_FIFO = 1'b1,
|
||||
@@ -66,6 +71,13 @@ module taxi_eth_mac_1g_gmii_fifo #
|
||||
output wire logic gmii_tx_en,
|
||||
output wire logic gmii_tx_er,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
@@ -83,8 +95,10 @@ module taxi_eth_mac_1g_gmii_fifo #
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [7:0] cfg_ifg = 8'd12,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
|
||||
input wire logic cfg_rx_enable = 1'b1
|
||||
);
|
||||
|
||||
@@ -177,6 +191,8 @@ always @(posedge logic_clk) begin
|
||||
link_speed_sync_reg_2 <= link_speed_sync_reg_1;
|
||||
end
|
||||
|
||||
wire stat_rx_fifo_drop;
|
||||
|
||||
taxi_eth_mac_1g_gmii #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
@@ -185,7 +201,12 @@ taxi_eth_mac_1g_gmii #(
|
||||
.MIN_FRAME_LEN(MIN_FRAME_LEN),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PFC_EN(1'b0),
|
||||
.PAUSE_EN(1'b0)
|
||||
.PAUSE_EN(1'b0),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
|
||||
)
|
||||
eth_mac_1g_gmii_inst (
|
||||
.gtx_clk(gtx_clk),
|
||||
@@ -250,14 +271,46 @@ eth_mac_1g_gmii_inst (
|
||||
.tx_pause_req(0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
// .rx_error_bad_frame(rx_error_bad_frame_int),
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(tx_error_underflow_int),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(tx_error_underflow_int),
|
||||
.rx_start_packet(),
|
||||
.rx_error_bad_frame(rx_error_bad_frame_int),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.link_speed(link_speed_int),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
@@ -281,8 +334,10 @@ eth_mac_1g_gmii_inst (
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(cfg_ifg),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast('0),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('0),
|
||||
@@ -445,7 +500,7 @@ rx_fifo (
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_overflow(stat_rx_fifo_drop),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
|
||||
@@ -26,7 +26,12 @@ module taxi_eth_mac_1g_rgmii #
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter PTP_TS_W = 96,
|
||||
parameter logic PFC_EN = 1'b0,
|
||||
parameter logic PAUSE_EN = PFC_EN
|
||||
parameter logic PAUSE_EN = PFC_EN,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024
|
||||
)
|
||||
(
|
||||
input wire logic gtx_clk,
|
||||
@@ -89,14 +94,45 @@ module taxi_eth_mac_1g_rgmii #
|
||||
input wire logic tx_pause_req = 1'b0,
|
||||
output wire logic tx_pause_ack,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic tx_start_packet,
|
||||
output wire logic tx_error_underflow,
|
||||
output wire logic stat_tx_byte,
|
||||
output wire logic [15:0] stat_tx_pkt_len,
|
||||
output wire logic stat_tx_pkt_ucast,
|
||||
output wire logic stat_tx_pkt_mcast,
|
||||
output wire logic stat_tx_pkt_bcast,
|
||||
output wire logic stat_tx_pkt_vlan,
|
||||
output wire logic stat_tx_pkt_good,
|
||||
output wire logic stat_tx_pkt_bad,
|
||||
output wire logic stat_tx_err_oversize,
|
||||
output wire logic stat_tx_err_user,
|
||||
output wire logic stat_tx_err_underflow,
|
||||
output wire logic rx_start_packet,
|
||||
output wire logic rx_error_bad_frame,
|
||||
output wire logic rx_error_bad_fcs,
|
||||
output wire logic stat_rx_byte,
|
||||
output wire logic [15:0] stat_rx_pkt_len,
|
||||
output wire logic stat_rx_pkt_fragment,
|
||||
output wire logic stat_rx_pkt_jabber,
|
||||
output wire logic stat_rx_pkt_ucast,
|
||||
output wire logic stat_rx_pkt_mcast,
|
||||
output wire logic stat_rx_pkt_bcast,
|
||||
output wire logic stat_rx_pkt_vlan,
|
||||
output wire logic stat_rx_pkt_good,
|
||||
output wire logic stat_rx_pkt_bad,
|
||||
output wire logic stat_rx_err_oversize,
|
||||
output wire logic stat_rx_err_bad_fcs,
|
||||
output wire logic stat_rx_err_bad_block,
|
||||
output wire logic stat_rx_err_framing,
|
||||
output wire logic stat_rx_err_preamble,
|
||||
input wire logic stat_rx_fifo_drop = 1'b0,
|
||||
output wire logic [1:0] link_speed,
|
||||
output wire logic stat_tx_mcf,
|
||||
output wire logic stat_rx_mcf,
|
||||
@@ -120,8 +156,10 @@ module taxi_eth_mac_1g_rgmii #
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [7:0] cfg_ifg = 8'd12,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
|
||||
input wire logic cfg_rx_enable = 1'b1,
|
||||
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
|
||||
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
|
||||
@@ -301,7 +339,12 @@ taxi_eth_mac_1g #(
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN)
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
|
||||
)
|
||||
eth_mac_1g_inst (
|
||||
.tx_clk(tx_clk),
|
||||
@@ -369,14 +412,45 @@ eth_mac_1g_inst (
|
||||
.rx_mii_select(rx_mii_select_sync),
|
||||
.tx_mii_select(tx_mii_select_sync),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.tx_error_underflow(tx_error_underflow),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_bad_frame(rx_error_bad_frame),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
@@ -399,8 +473,10 @@ eth_mac_1g_inst (
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(cfg_ifg),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
|
||||
@@ -23,6 +23,11 @@ module taxi_eth_mac_1g_rgmii_fifo #
|
||||
parameter logic USE_CLK90 = 1'b1,
|
||||
parameter logic PADDING_EN = 1'b1,
|
||||
parameter MIN_FRAME_LEN = 64,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter TX_FIFO_DEPTH = 4096,
|
||||
parameter TX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic TX_FRAME_FIFO = 1'b1,
|
||||
@@ -65,6 +70,13 @@ module taxi_eth_mac_1g_rgmii_fifo #
|
||||
output wire logic [3:0] rgmii_txd,
|
||||
output wire logic rgmii_tx_ctl,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
@@ -82,8 +94,10 @@ module taxi_eth_mac_1g_rgmii_fifo #
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [7:0] cfg_ifg = 8'd12,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
|
||||
input wire logic cfg_rx_enable = 1'b1
|
||||
);
|
||||
|
||||
@@ -176,6 +190,8 @@ always @(posedge logic_clk) begin
|
||||
link_speed_sync_reg_2 <= link_speed_sync_reg_1;
|
||||
end
|
||||
|
||||
wire stat_rx_fifo_drop;
|
||||
|
||||
taxi_eth_mac_1g_rgmii #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
@@ -185,7 +201,12 @@ taxi_eth_mac_1g_rgmii #(
|
||||
.MIN_FRAME_LEN(MIN_FRAME_LEN),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PFC_EN(1'b0),
|
||||
.PAUSE_EN(1'b0)
|
||||
.PAUSE_EN(1'b0),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
|
||||
)
|
||||
eth_mac_1g_rgmii_inst (
|
||||
.gtx_clk(gtx_clk),
|
||||
@@ -248,14 +269,46 @@ eth_mac_1g_rgmii_inst (
|
||||
.tx_pause_req(0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
// .rx_error_bad_frame(rx_error_bad_frame_int),
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(tx_error_underflow_int),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(tx_error_underflow_int),
|
||||
.rx_start_packet(),
|
||||
.rx_error_bad_frame(rx_error_bad_frame_int),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.link_speed(link_speed_int),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
@@ -279,8 +332,10 @@ eth_mac_1g_rgmii_inst (
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(cfg_ifg),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast('0),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('0),
|
||||
@@ -443,7 +498,7 @@ rx_fifo (
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_overflow(stat_rx_fifo_drop),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
|
||||
@@ -25,7 +25,12 @@ module taxi_eth_mac_mii #
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter PTP_TS_W = 96,
|
||||
parameter logic PFC_EN = 1'b0,
|
||||
parameter logic PAUSE_EN = PFC_EN
|
||||
parameter logic PAUSE_EN = PFC_EN,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024
|
||||
)
|
||||
(
|
||||
input wire logic rst,
|
||||
@@ -88,14 +93,45 @@ module taxi_eth_mac_mii #
|
||||
input wire logic tx_pause_req = 1'b0,
|
||||
output wire logic tx_pause_ack,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic tx_start_packet,
|
||||
output wire logic tx_error_underflow,
|
||||
output wire logic stat_tx_byte,
|
||||
output wire logic [15:0] stat_tx_pkt_len,
|
||||
output wire logic stat_tx_pkt_ucast,
|
||||
output wire logic stat_tx_pkt_mcast,
|
||||
output wire logic stat_tx_pkt_bcast,
|
||||
output wire logic stat_tx_pkt_vlan,
|
||||
output wire logic stat_tx_pkt_good,
|
||||
output wire logic stat_tx_pkt_bad,
|
||||
output wire logic stat_tx_err_oversize,
|
||||
output wire logic stat_tx_err_user,
|
||||
output wire logic stat_tx_err_underflow,
|
||||
output wire logic rx_start_packet,
|
||||
output wire logic rx_error_bad_frame,
|
||||
output wire logic rx_error_bad_fcs,
|
||||
output wire logic stat_rx_byte,
|
||||
output wire logic [15:0] stat_rx_pkt_len,
|
||||
output wire logic stat_rx_pkt_fragment,
|
||||
output wire logic stat_rx_pkt_jabber,
|
||||
output wire logic stat_rx_pkt_ucast,
|
||||
output wire logic stat_rx_pkt_mcast,
|
||||
output wire logic stat_rx_pkt_bcast,
|
||||
output wire logic stat_rx_pkt_vlan,
|
||||
output wire logic stat_rx_pkt_good,
|
||||
output wire logic stat_rx_pkt_bad,
|
||||
output wire logic stat_rx_err_oversize,
|
||||
output wire logic stat_rx_err_bad_fcs,
|
||||
output wire logic stat_rx_err_bad_block,
|
||||
output wire logic stat_rx_err_framing,
|
||||
output wire logic stat_rx_err_preamble,
|
||||
input wire logic stat_rx_fifo_drop = 1'b0,
|
||||
output wire logic stat_tx_mcf,
|
||||
output wire logic stat_rx_mcf,
|
||||
output wire logic stat_tx_lfc_pkt,
|
||||
@@ -118,8 +154,10 @@ module taxi_eth_mac_mii #
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [7:0] cfg_ifg = 8'd12,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
|
||||
input wire logic cfg_rx_enable = 1'b1,
|
||||
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
|
||||
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
|
||||
@@ -205,7 +243,12 @@ taxi_eth_mac_1g #(
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN)
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
|
||||
)
|
||||
eth_mac_1g_inst (
|
||||
.tx_clk(tx_clk),
|
||||
@@ -273,14 +316,45 @@ eth_mac_1g_inst (
|
||||
.rx_mii_select(1'b1),
|
||||
.tx_mii_select(1'b1),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.tx_error_underflow(tx_error_underflow),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_bad_frame(rx_error_bad_frame),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
@@ -303,8 +377,10 @@ eth_mac_1g_inst (
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(cfg_ifg),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
|
||||
@@ -22,6 +22,11 @@ module taxi_eth_mac_mii_fifo #
|
||||
parameter string FAMILY = "virtex7",
|
||||
parameter logic PADDING_EN = 1'b1,
|
||||
parameter MIN_FRAME_LEN = 64,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter TX_FIFO_DEPTH = 4096,
|
||||
parameter TX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic TX_FRAME_FIFO = 1'b1,
|
||||
@@ -64,6 +69,13 @@ module taxi_eth_mac_mii_fifo #
|
||||
output wire mii_tx_en,
|
||||
output wire mii_tx_er,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
@@ -80,8 +92,10 @@ module taxi_eth_mac_mii_fifo #
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [7:0] cfg_ifg = 8'd12,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
|
||||
input wire logic cfg_rx_enable = 1'b1
|
||||
);
|
||||
|
||||
@@ -162,6 +176,8 @@ always_ff @(posedge logic_clk or posedge logic_rst) begin
|
||||
end
|
||||
end
|
||||
|
||||
wire stat_rx_fifo_drop;
|
||||
|
||||
taxi_eth_mac_mii #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
@@ -170,7 +186,12 @@ taxi_eth_mac_mii #(
|
||||
.MIN_FRAME_LEN(MIN_FRAME_LEN),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PFC_EN(1'b0),
|
||||
.PAUSE_EN(1'b0)
|
||||
.PAUSE_EN(1'b0),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
|
||||
)
|
||||
eth_mac_mii_inst (
|
||||
.rst(rst),
|
||||
@@ -233,14 +254,46 @@ eth_mac_mii_inst (
|
||||
.tx_pause_req(0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
// .rx_error_bad_frame(rx_error_bad_frame_int),
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(tx_error_underflow_int),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(tx_error_underflow_int),
|
||||
.rx_start_packet(),
|
||||
.rx_error_bad_frame(rx_error_bad_frame_int),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
@@ -263,8 +316,10 @@ eth_mac_mii_inst (
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg(cfg_ifg),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast('0),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('0),
|
||||
@@ -427,7 +482,7 @@ rx_fifo (
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_overflow(stat_rx_fifo_drop),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
|
||||
Reference in New Issue
Block a user