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eth: Add MAC statistics module to 1G MACs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-08 20:22:53 -07:00
parent bb90cd5a08
commit e90340db6e
33 changed files with 1453 additions and 192 deletions
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5
tb/eth/taxi_eth_mac_1g_rgmii_fifo/Makefile
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@@ -36,6 +36,11 @@ export PARAM_AXIS_DATA_W := 8
export PARAM_PADDING_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_TX_TAG_W := 16
export PARAM_STAT_EN := 1
export PARAM_STAT_TX_LEVEL := 2
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
export PARAM_STAT_ID_BASE := 0
export PARAM_STAT_UPDATE_PERIOD := 1024
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1

21
tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py
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@@ -32,6 +32,7 @@ class TB:
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
self.rgmii_phy = RgmiiPhy(dut.rgmii_txd, dut.rgmii_tx_ctl, dut.rgmii_tx_clk,
dut.rgmii_rxd, dut.rgmii_rx_ctl, dut.rgmii_rx_clk, speed=speed)
@@ -40,8 +41,12 @@ class TB:
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.gtx_clk.setimmediatevalue(0)
@@ -52,14 +57,17 @@ class TB:
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
self.dut.logic_rst.setimmediatevalue(0)
self.dut.stat_rst.setimmediatevalue(0)
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 1
self.dut.logic_rst.value = 1
self.dut.stat_rst.value = 1
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
self.dut.gtx_rst.value = 0
self.dut.logic_rst.value = 0
self.dut.stat_rst.value = 0
await RisingEdge(self.dut.gtx_clk)
await RisingEdge(self.dut.gtx_clk)
@@ -81,7 +89,8 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_rx_max_pkt_len.value = 9218
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@@ -119,7 +128,8 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb = TB(dut, speed)
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@@ -217,6 +227,11 @@ def test_taxi_eth_mac_1g_rgmii_fifo(request):
parameters['PADDING_EN'] = 1
parameters['MIN_FRAME_LEN'] = 64
parameters['TX_TAG_W'] = 16
parameters['STAT_EN'] = 1
parameters['STAT_TX_LEVEL'] = 2
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
parameters['STAT_ID_BASE'] = 0
parameters['STAT_UPDATE_PERIOD'] = 1024
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1

29
tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
View File

@@ -26,6 +26,11 @@ module test_taxi_eth_mac_1g_rgmii_fifo #
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_TAG_W = 16,
parameter logic STAT_EN = 1'b0,
parameter STAT_TX_LEVEL = 1,
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
parameter STAT_ID_BASE = 0,
parameter STAT_UPDATE_PERIOD = 1024,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
@@ -64,6 +69,10 @@ logic rgmii_tx_clk;
logic [3:0] rgmii_txd;
logic rgmii_tx_ctl;
logic stat_clk;
logic stat_rst;
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
@@ -75,8 +84,10 @@ logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [1:0] link_speed;
logic [7:0] cfg_ifg;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic [15:0] cfg_rx_max_pkt_len;
logic cfg_rx_enable;
taxi_eth_mac_1g_rgmii_fifo #(
@@ -86,6 +97,11 @@ taxi_eth_mac_1g_rgmii_fifo #(
.USE_CLK90(USE_CLK90),
.PADDING_EN(PADDING_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.STAT_EN(STAT_EN),
.STAT_TX_LEVEL(STAT_TX_LEVEL),
.STAT_RX_LEVEL(STAT_RX_LEVEL),
.STAT_ID_BASE(STAT_ID_BASE),
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
@@ -128,6 +144,13 @@ uut (
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
/*
* Statistics
*/
.stat_clk(stat_clk),
.stat_rst(stat_rst),
.m_axis_stat(m_axis_stat),
/*
* Status
*/
@@ -145,8 +168,10 @@ uut (
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
.cfg_rx_enable(cfg_rx_enable)
);