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eth: Add 32-bit AXI stream BASE-R TX module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-06-17 20:14:30 -07:00
parent 6f5adb1b41
commit ebb8bf0bd4
5 changed files with 1586 additions and 0 deletions
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream 10GBASE-R frame transmitter (AXI in, 10GBASE-R out)
*/
module taxi_axis_baser_tx_32 #
(
parameter DATA_W = 32,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter GBX_CNT = 1,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96,
parameter logic TX_CPL_CTRL_IN_TUSER = 1'b1
)
(
input wire logic clk,
input wire logic rst,
/*
* Transmit interface (AXI stream)
*/
taxi_axis_if.snk s_axis_tx,
taxi_axis_if.src m_axis_tx_cpl,
/*
* 10GBASE-R encoded interface
*/
output wire logic [DATA_W-1:0] encoded_tx_data,
output wire logic encoded_tx_data_valid,
output wire logic [HDR_W-1:0] encoded_tx_hdr,
output wire logic encoded_tx_hdr_valid,
input wire logic [GBX_CNT-1:0] tx_gbx_req_sync = '0,
input wire logic tx_gbx_req_stall = '0,
output wire logic [GBX_CNT-1:0] tx_gbx_sync,
/*
* PTP
*/
input wire logic [PTP_TS_W-1:0] ptp_ts,
/*
* Configuration
*/
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
input wire logic [7:0] cfg_tx_ifg = 8'd12,
input wire logic cfg_tx_enable,
/*
* Status
*/
output wire logic tx_start_packet,
output wire logic [2:0] stat_tx_byte,
output wire logic [15:0] stat_tx_pkt_len,
output wire logic stat_tx_pkt_ucast,
output wire logic stat_tx_pkt_mcast,
output wire logic stat_tx_pkt_bcast,
output wire logic stat_tx_pkt_vlan,
output wire logic stat_tx_pkt_good,
output wire logic stat_tx_pkt_bad,
output wire logic stat_tx_err_oversize,
output wire logic stat_tx_err_user,
output wire logic stat_tx_err_underflow
);
// extract parameters
localparam KEEP_W = DATA_W/8;
localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
localparam TX_TAG_W = s_axis_tx.ID_W;
localparam EMPTY_W = $clog2(KEEP_W);
localparam MIN_LEN_W = $clog2(MIN_FRAME_LEN-4-KEEP_W+1);
// check configuration
if (DATA_W != 32)
$fatal(0, "Error: Interface width must be 32 (instance %m)");
if (KEEP_W*8 != DATA_W)
$fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2 (instance %m)");
if (s_axis_tx.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (s_axis_tx.USER_W != USER_W)
$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
localparam [2:0]
OUTPUT_TYPE_IDLE = 3'd0,
OUTPUT_TYPE_ERROR = 3'd1,
OUTPUT_TYPE_START = 3'd2,
OUTPUT_TYPE_DATA = 3'd3,
OUTPUT_TYPE_TERM_0 = 3'd4,
OUTPUT_TYPE_TERM_1 = 3'd5,
OUTPUT_TYPE_TERM_2 = 3'd6,
OUTPUT_TYPE_TERM_3 = 3'd7;
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_PREAMBLE = 4'd1,
STATE_PAYLOAD = 4'd2,
STATE_PAD = 4'd3,
STATE_FCS_1 = 4'd4,
STATE_FCS_2 = 4'd5,
STATE_FCS_3 = 4'd6,
STATE_ERR = 4'd7,
STATE_IFG = 4'd8;
logic [3:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;
logic update_crc;
logic [DATA_W-1:0] s_tdata_reg = '0, s_tdata_next;
logic [EMPTY_W-1:0] s_empty_reg = '0, s_empty_next;
logic [DATA_W-1:0] fcs_output_data_0;
logic [DATA_W-1:0] fcs_output_data_1;
logic [2:0] fcs_output_type_0;
logic [2:0] fcs_output_type_1;
logic [7:0] ifg_offset;
logic extra_cycle;
logic frame_reg = 1'b0, frame_next;
logic frame_error_reg = 1'b0, frame_error_next;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic [MIN_LEN_W-1:0] frame_min_count_reg = '0, frame_min_count_next;
logic [2:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
logic [15:0] frame_len_reg = '0, frame_len_next;
logic [15:0] frame_len_lim_reg = '0, frame_len_lim_next;
logic [7:0] ifg_cnt_reg = '0, ifg_cnt_next;
logic [7:0] ifg_count_reg = 8'd0, ifg_count_next;
logic [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
logic s_axis_tx_tready_reg = 1'b0, s_axis_tx_tready_next;
logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0, m_axis_tx_cpl_ts_next;
logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic [31:0] crc_state_reg[3:0];
wire [31:0] crc_state_next[3:0];
logic [DATA_W-1:0] encoded_tx_data_reg = {24'd0, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
logic encoded_tx_hdr_valid_reg = 1'b0;
logic phase_reg = 1'b0;
logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0;
logic [DATA_W-1:0] output_data_reg = '0, output_data_next;
logic [DATA_W-1:0] output_data_d1_reg = '0;
logic [2:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
logic start_packet_reg = 1'b0, start_packet_next;
logic [2:0] stat_tx_byte_reg = '0, stat_tx_byte_next;
logic [15:0] stat_tx_pkt_len_reg = '0, stat_tx_pkt_len_next;
logic stat_tx_pkt_ucast_reg = 1'b0, stat_tx_pkt_ucast_next;
logic stat_tx_pkt_mcast_reg = 1'b0, stat_tx_pkt_mcast_next;
logic stat_tx_pkt_bcast_reg = 1'b0, stat_tx_pkt_bcast_next;
logic stat_tx_pkt_vlan_reg = 1'b0, stat_tx_pkt_vlan_next;
logic stat_tx_pkt_good_reg = 1'b0, stat_tx_pkt_good_next;
logic stat_tx_pkt_bad_reg = 1'b0, stat_tx_pkt_bad_next;
logic stat_tx_err_oversize_reg = 1'b0, stat_tx_err_oversize_next;
logic stat_tx_err_user_reg = 1'b0, stat_tx_err_user_next;
logic stat_tx_err_underflow_reg = 1'b0, stat_tx_err_underflow_next;
assign s_axis_tx.tready = s_axis_tx_tready_reg && (!GBX_IF_EN || !tx_gbx_req_stall);
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_data_valid = GBX_IF_EN ? encoded_tx_data_valid_reg : 1'b1;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign encoded_tx_hdr_valid = encoded_tx_hdr_valid_reg;
assign tx_gbx_sync = GBX_IF_EN ? tx_gbx_sync_reg : '0;
assign m_axis_tx_cpl.tdata = PTP_TS_EN ? m_axis_tx_cpl_ts_reg : '0;
assign m_axis_tx_cpl.tkeep = 1'b1;
assign m_axis_tx_cpl.tstrb = m_axis_tx_cpl.tkeep;
assign m_axis_tx_cpl.tvalid = m_axis_tx_cpl_valid_reg;
assign m_axis_tx_cpl.tlast = 1'b1;
assign m_axis_tx_cpl.tid = m_axis_tx_cpl_tag_reg;
assign m_axis_tx_cpl.tdest = '0;
assign m_axis_tx_cpl.tuser = '0;
assign tx_start_packet = start_packet_reg;
assign stat_tx_byte = stat_tx_byte_reg;
assign stat_tx_pkt_len = stat_tx_pkt_len_reg;
assign stat_tx_pkt_ucast = stat_tx_pkt_ucast_reg;
assign stat_tx_pkt_mcast = stat_tx_pkt_mcast_reg;
assign stat_tx_pkt_bcast = stat_tx_pkt_bcast_reg;
assign stat_tx_pkt_vlan = stat_tx_pkt_vlan_reg;
assign stat_tx_pkt_good = stat_tx_pkt_good_reg;
assign stat_tx_pkt_bad = stat_tx_pkt_bad_reg;
assign stat_tx_err_oversize = stat_tx_err_oversize_reg;
assign stat_tx_err_user = stat_tx_err_user_reg;
assign stat_tx_err_underflow = stat_tx_err_underflow_reg;
for (genvar n = 0; n < 4; n = n + 1) begin : crc
taxi_lfsr #(
.LFSR_W(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_GALOIS(1),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_W(8*(n+1)),
.DATA_IN_EN(1'b1),
.DATA_OUT_EN(1'b0)
)
eth_crc (
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[3]),
.data_out(),
.state_out(crc_state_next[n])
);
end
function [1:0] keep2empty(input [3:0] k);
casez (k)
4'bzzz0: keep2empty = 2'd3;
4'bzz01: keep2empty = 2'd3;
4'bz011: keep2empty = 2'd2;
4'b0111: keep2empty = 2'd1;
4'b1111: keep2empty = 2'd0;
endcase
endfunction
// Mask input data
wire [DATA_W-1:0] s_axis_tx_tdata_masked;
for (genvar n = 0; n < KEEP_W; n = n + 1) begin
assign s_axis_tx_tdata_masked[n*8 +: 8] = s_axis_tx.tkeep[n] ? s_axis_tx.tdata[n*8 +: 8] : 8'd0;
end
// FCS cycle calculation
always_comb begin
casez (s_empty_reg)
2'd3: begin
fcs_output_data_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]};
fcs_output_data_1 = {24'd0, ~crc_state_reg[0][31:24]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_1;
ifg_offset = 8'd3;
extra_cycle = 1'b0;
end
2'd2: begin
fcs_output_data_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]};
fcs_output_data_1 = {16'd0, ~crc_state_reg[1][31:16]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_2;
ifg_offset = 8'd2;
extra_cycle = 1'b0;
end
2'd1: begin
fcs_output_data_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]};
fcs_output_data_1 = {8'd0, ~crc_state_reg[2][31:8]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_3;
ifg_offset = 8'd1;
extra_cycle = 1'b0;
end
2'd0: begin
fcs_output_data_0 = s_tdata_reg;
fcs_output_data_1 = ~crc_state_reg[3];
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_DATA;
ifg_offset = 8'd4;
extra_cycle = 1'b1;
end
endcase
end
always_comb begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
frame_next = frame_reg;
frame_error_next = frame_error_reg;
frame_oversize_next = frame_oversize_reg;
frame_min_count_next = frame_min_count_reg;
hdr_ptr_next = hdr_ptr_reg;
is_mcast_next = is_mcast_reg;
is_bcast_next = is_bcast_reg;
is_8021q_next = is_8021q_reg;
frame_len_next = frame_len_reg;
frame_len_lim_next = frame_len_lim_reg;
ifg_cnt_next = ifg_cnt_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tx_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_empty_next = s_empty_reg;
m_axis_tx_cpl_ts_next = m_axis_tx_cpl_ts_reg;
m_axis_tx_cpl_tag_next = m_axis_tx_cpl_tag_reg;
m_axis_tx_cpl_valid_next = 1'b0;
if (start_packet_reg) begin
if (PTP_TS_EN) begin
m_axis_tx_cpl_ts_next = ptp_ts;
end
m_axis_tx_cpl_tag_next = s_axis_tx.tid;
if (TX_CPL_CTRL_IN_TUSER) begin
m_axis_tx_cpl_valid_next = (s_axis_tx.tuser >> 1) == 0;
end else begin
m_axis_tx_cpl_valid_next = 1'b1;
end
end
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
start_packet_next = 1'b0;
stat_tx_byte_next = '0;
stat_tx_pkt_len_next = '0;
stat_tx_pkt_ucast_next = 1'b0;
stat_tx_pkt_mcast_next = 1'b0;
stat_tx_pkt_bcast_next = 1'b0;
stat_tx_pkt_vlan_next = 1'b0;
stat_tx_pkt_good_next = 1'b0;
stat_tx_pkt_bad_next = 1'b0;
stat_tx_err_oversize_next = 1'b0;
stat_tx_err_user_next = 1'b0;
stat_tx_err_underflow_next = 1'b0;
if (s_axis_tx.tvalid && s_axis_tx.tready) begin
frame_next = !s_axis_tx.tlast;
end
if (GBX_IF_EN && tx_gbx_req_stall) begin
// gearbox stall - hold state
state_next = state_reg;
s_axis_tx_tready_next = s_axis_tx_tready_reg;
end else begin
// counter for min frame length enforcement
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
frame_min_count_next = MIN_LEN_W'(frame_min_count_reg - KEEP_W);
end else begin
frame_min_count_next = 0;
end
// counter to measure frame length
if (&frame_len_reg[15:2] == 0) begin
frame_len_next = frame_len_reg + 16'(KEEP_W);
end else begin
frame_len_next = '1;
end
// counter for max frame length enforcement
if (frame_len_lim_reg[15:2] != 0) begin
frame_len_lim_next = frame_len_lim_reg - 16'(KEEP_W);
end else begin
frame_len_lim_next = '0;
end
// address and ethertype checks
if (&hdr_ptr_reg == 0) begin
hdr_ptr_next = hdr_ptr_reg + 1;
end
case (hdr_ptr_reg)
3'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = &s_tdata_reg;
end
3'd1: is_bcast_next = is_bcast_reg && &s_tdata_reg[15:0];
3'd3: is_8021q_next = {s_tdata_reg[7:0], s_tdata_reg[15:8]} == 16'h8100;
default: begin
// do nothing
end
endcase
if (ifg_cnt_reg[7:2] != 0) begin
ifg_cnt_next = ifg_cnt_reg - 8'(KEEP_W);
end else begin
ifg_cnt_next = '0;
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_error_next = 1'b0;
frame_min_count_next = MIN_LEN_W'(MIN_FRAME_LEN-4-KEEP_W);
hdr_ptr_next = 0;
frame_len_next = 0;
frame_len_lim_next = cfg_tx_max_pkt_len;
reset_crc = 1'b1;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
if (s_axis_tx.tvalid && cfg_tx_enable) begin
// Preamble and SFD
output_data_next = {4{ETH_PRE}};
output_type_next = OUTPUT_TYPE_START;
s_axis_tx_tready_next = 1'b1;
state_next = STATE_PREAMBLE;
end else begin
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
// send preamble
reset_crc = 1'b1;
hdr_ptr_next = 0;
frame_len_next = 0;
frame_len_lim_next = cfg_tx_max_pkt_len;
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
output_data_next = {ETH_SFD, {3{ETH_PRE}}};
output_type_next = OUTPUT_TYPE_DATA;
s_axis_tx_tready_next = 1'b1;
start_packet_next = 1'b1;
state_next = STATE_PAYLOAD;
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tx_tready_next = 1'b1;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
stat_tx_byte_next = 3'(KEEP_W);
if (s_axis_tx.tvalid && s_axis_tx.tlast) begin
frame_oversize_next = frame_len_lim_reg < 16'(4+4+4-keep2empty(s_axis_tx.tkeep));
end else begin
frame_oversize_next = frame_len_lim_reg < 4+4;
end
if (!s_axis_tx.tvalid || s_axis_tx.tlast || frame_oversize_next) begin
s_axis_tx_tready_next = frame_next; // drop frame
frame_error_next = !s_axis_tx.tvalid || s_axis_tx.tuser[0] || frame_oversize_next;
stat_tx_err_user_next = s_axis_tx.tuser[0];
stat_tx_err_underflow_next = !s_axis_tx.tvalid;
if (PADDING_EN && frame_min_count_reg != 0) begin
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
s_empty_next = 0;
state_next = STATE_PAD;
end else begin
if (keep2empty(s_axis_tx.tkeep) > 2'(KEEP_W-frame_min_count_reg)) begin
s_empty_next = 2'(KEEP_W-frame_min_count_reg);
end
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LEN
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = 32'd0;
s_empty_next = 0;
stat_tx_byte_next = 3'(KEEP_W);
update_crc = 1'b1;
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
state_next = STATE_PAD;
end else begin
s_empty_next = 2'(KEEP_W-frame_min_count_reg);
state_next = STATE_FCS_1;
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
stat_tx_byte_next = 3'(KEEP_W);
update_crc = 1'b1;
ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + 8'(deficit_idle_count_reg);
if (frame_error_reg) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_2;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = fcs_output_data_1;
output_type_next = fcs_output_type_1;
stat_tx_byte_next = 4-s_empty_reg;
frame_len_next = frame_len_reg + 16'(4-s_empty_reg);
if (extra_cycle) begin
state_next = STATE_FCS_3;
end else begin
stat_tx_pkt_len_next = frame_len_next;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
state_next = STATE_IFG;
end
end
STATE_FCS_3: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_TERM_0;
stat_tx_pkt_len_next = frame_len_reg;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
if (DIC_EN) begin
if (ifg_count_next > 8'd3) begin
state_next = STATE_IFG;
end else begin
deficit_idle_count_next = 2'(ifg_count_next);
ifg_count_next = 8'd0;
s_axis_tx_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd0) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
end
STATE_ERR: begin
// terminate packet with error
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_ERROR;
ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12;
stat_tx_pkt_len_next = frame_len_reg;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
state_next = STATE_IFG;
end
STATE_IFG: begin
// send IFG
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
if (ifg_count_reg > 8'd4) begin
ifg_count_next = ifg_count_reg - 8'd4;
end else begin
ifg_count_next = 8'd0;
end
if (DIC_EN) begin
if (ifg_count_next > 8'd3 || frame_reg) begin
state_next = STATE_IFG;
end else begin
deficit_idle_count_next = 2'(ifg_count_next);
ifg_count_next = 8'd0;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd0 || frame_reg) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
end
default: begin
// invalid state, return to idle
state_next = STATE_IDLE;
end
endcase
end
end
always_ff @(posedge clk) begin
state_reg <= state_next;
frame_reg <= frame_next;
frame_error_reg <= frame_error_next;
frame_oversize_reg <= frame_oversize_next;
frame_min_count_reg <= frame_min_count_next;
hdr_ptr_reg <= hdr_ptr_next;
is_mcast_reg <= is_mcast_next;
is_bcast_reg <= is_bcast_next;
is_8021q_reg <= is_8021q_next;
frame_len_reg <= frame_len_next;
frame_len_lim_reg <= frame_len_lim_next;
ifg_cnt_reg <= ifg_cnt_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_tdata_reg <= s_tdata_next;
s_empty_reg <= s_empty_next;
s_axis_tx_tready_reg <= s_axis_tx_tready_next;
m_axis_tx_cpl_ts_reg <= m_axis_tx_cpl_ts_next;
m_axis_tx_cpl_tag_reg <= m_axis_tx_cpl_tag_next;
m_axis_tx_cpl_valid_reg <= m_axis_tx_cpl_valid_next;
start_packet_reg <= start_packet_next;
stat_tx_byte_reg <= stat_tx_byte_next;
stat_tx_pkt_len_reg <= stat_tx_pkt_len_next;
stat_tx_pkt_ucast_reg <= stat_tx_pkt_ucast_next;
stat_tx_pkt_mcast_reg <= stat_tx_pkt_mcast_next;
stat_tx_pkt_bcast_reg <= stat_tx_pkt_bcast_next;
stat_tx_pkt_vlan_reg <= stat_tx_pkt_vlan_next;
stat_tx_pkt_good_reg <= stat_tx_pkt_good_next;
stat_tx_pkt_bad_reg <= stat_tx_pkt_bad_next;
stat_tx_err_oversize_reg <= stat_tx_err_oversize_next;
stat_tx_err_user_reg <= stat_tx_err_user_next;
stat_tx_err_underflow_reg <= stat_tx_err_underflow_next;
if (GBX_IF_EN && tx_gbx_req_stall) begin
// gearbox stall
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_valid_reg <= 1'b0;
end else begin
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
output_data_d1_reg <= output_data_reg;
if (phase_reg == 0) begin
case ({output_type_reg, output_type_next})
{OUTPUT_TYPE_IDLE, OUTPUT_TYPE_IDLE}: begin
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_ERROR, OUTPUT_TYPE_ERROR}: begin
encoded_tx_data_reg <= {24'hc78f1e, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_START, OUTPUT_TYPE_DATA}: begin
encoded_tx_data_reg <= {output_data_reg[31:8], BLOCK_TYPE_START_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_IDLE, OUTPUT_TYPE_START}: begin
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_START_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_DATA, OUTPUT_TYPE_DATA}: begin
encoded_tx_data_reg <= output_data_reg;
encoded_tx_hdr_reg <= SYNC_DATA;
end
{OUTPUT_TYPE_TERM_0, OUTPUT_TYPE_IDLE}: begin
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_TERM_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_TERM_1, OUTPUT_TYPE_IDLE}: begin
encoded_tx_data_reg <= {16'd0, output_data_reg[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_TERM_2, OUTPUT_TYPE_IDLE}: begin
encoded_tx_data_reg <= {8'd0, output_data_reg[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_TERM_3, OUTPUT_TYPE_IDLE}: begin
encoded_tx_data_reg <= {output_data_reg[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_DATA, OUTPUT_TYPE_TERM_0}: begin
encoded_tx_data_reg <= {output_data_reg[23:0], BLOCK_TYPE_TERM_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_DATA, OUTPUT_TYPE_TERM_1}: begin
encoded_tx_data_reg <= {output_data_reg[23:0], BLOCK_TYPE_TERM_5};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_DATA, OUTPUT_TYPE_TERM_2}: begin
encoded_tx_data_reg <= {output_data_reg[23:0], BLOCK_TYPE_TERM_6};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_DATA, OUTPUT_TYPE_TERM_3}: begin
encoded_tx_data_reg <= {output_data_reg[23:0], BLOCK_TYPE_TERM_7};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
default: begin
encoded_tx_data_reg <= {24'hc78f1e, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
endcase
end else begin
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= 32'd0;
end
OUTPUT_TYPE_ERROR: begin
encoded_tx_data_reg <= 32'h3c78f1e3; // CTRL_ERROR
end
OUTPUT_TYPE_START: begin
encoded_tx_data_reg <= {output_data_reg[31:8], 8'd0};
end
OUTPUT_TYPE_DATA: begin
encoded_tx_data_reg <= output_data_reg;
end
OUTPUT_TYPE_TERM_0: begin
encoded_tx_data_reg <= {24'd0, output_data_d1_reg[31:24]};
end
OUTPUT_TYPE_TERM_1: begin
encoded_tx_data_reg <= {16'd0, output_data_reg[7:0], output_data_d1_reg[31:24]};
end
OUTPUT_TYPE_TERM_2: begin
encoded_tx_data_reg <= {8'd0, output_data_reg[15:0], output_data_d1_reg[31:24]};
end
OUTPUT_TYPE_TERM_3: begin
encoded_tx_data_reg <= {output_data_reg[23:0], output_data_d1_reg[31:24]};
end
default: begin
encoded_tx_data_reg <= 32'h3c78f1e3; // CTRL_ERROR
end
endcase
end
encoded_tx_data_valid_reg <= 1'b1;
encoded_tx_hdr_valid_reg <= phase_reg == 0;
phase_reg <= !phase_reg;
if (GBX_IF_EN && tx_gbx_req_sync[0]) begin
phase_reg <= 1'b1;
end
for (integer i = 0; i < 3; i = i + 1) begin
crc_state_reg[i] <= crc_state_next[i];
end
if (update_crc) begin
crc_state_reg[3] <= crc_state_next[3];
end
if (reset_crc) begin
crc_state_reg[3] <= '1;
end
end
tx_gbx_sync_reg <= tx_gbx_req_sync;
if (rst) begin
state_reg <= STATE_IDLE;
frame_reg <= 1'b0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tx_tready_reg <= 1'b0;
m_axis_tx_cpl_valid_reg <= 1'b0;
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_CTRL};
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_reg <= SYNC_CTRL;
encoded_tx_hdr_valid_reg <= 1'b0;
phase_reg <= 1'b0;
tx_gbx_sync_reg <= '0;
output_type_reg <= OUTPUT_TYPE_IDLE;
start_packet_reg <= 1'b0;
stat_tx_byte_reg <= '0;
stat_tx_pkt_len_reg <= '0;
stat_tx_pkt_ucast_reg <= 1'b0;
stat_tx_pkt_mcast_reg <= 1'b0;
stat_tx_pkt_bcast_reg <= 1'b0;
stat_tx_pkt_vlan_reg <= 1'b0;
stat_tx_pkt_good_reg <= 1'b0;
stat_tx_pkt_bad_reg <= 1'b0;
stat_tx_err_oversize_reg <= 1'b0;
stat_tx_err_user_reg <= 1'b0;
stat_tx_err_underflow_reg <= 1'b0;
end
end
endmodule
`resetall

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src/eth/tb/taxi_axis_baser_tx_32/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_baser_tx_32
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_HDR_W := 2
export PARAM_GBX_IF_EN := 1
export PARAM_GBX_CNT := 1
export PARAM_PADDING_EN := 1
export PARAM_DIC_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_PTP_TS_EN := 1
export PARAM_PTP_TS_FMT_TOD := 1
export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
export PARAM_TX_TAG_W := 16
export PARAM_TX_CPL_CTRL_IN_TUSER := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

1
src/eth/tb/taxi_axis_baser_tx_32/baser.py Symbolic link
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../baser.py

491
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import sys
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.utils import get_time_from_sim_steps
from cocotb.regression import TestFactory
from cocotbext.eth import PtpClockSimTime
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
try:
from baser import BaseRSerdesSink
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from baser import BaseRSerdesSink
finally:
del sys.path[0]
class TB:
def __init__(self, dut, gbx_cfg=None):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
if gbx_cfg:
self.clk_period = 3.102
else:
self.clk_period = 3.2
cocotb.start_soon(Clock(dut.clk, self.clk_period, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
self.sink = BaseRSerdesSink(
data=dut.encoded_tx_data,
data_valid=dut.encoded_tx_data_valid,
hdr=dut.encoded_tx_hdr,
hdr_valid=dut.encoded_tx_hdr_valid,
gbx_req_sync=dut.tx_gbx_req_sync,
gbx_req_stall=dut.tx_gbx_req_stall,
gbx_sync=dut.tx_gbx_sync,
clock=dut.clk,
scramble=False,
gbx_cfg=gbx_cfg
)
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
self.stats = {}
self.stats["stat_tx_byte"] = 0
self.stats["stat_tx_pkt_len"] = 0
self.stats["stat_tx_pkt_ucast"] = 0
self.stats["stat_tx_pkt_mcast"] = 0
self.stats["stat_tx_pkt_bcast"] = 0
self.stats["stat_tx_pkt_vlan"] = 0
self.stats["stat_tx_pkt_good"] = 0
self.stats["stat_tx_pkt_bad"] = 0
self.stats["stat_tx_err_oversize"] = 0
self.stats["stat_tx_err_user"] = 0
self.stats["stat_tx_err_underflow"] = 0
cocotb.start_soon(self._run_stats_counters())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.stats_reset()
def stats_reset(self):
for stat in self.stats:
self.stats[stat] = 0
async def _run_stats_counters(self):
while True:
await RisingEdge(self.dut.clk)
for stat in self.stats:
self.stats[stat] += int(getattr(self.dut, stat).value)
async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut, gbx_cfg)
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
await tb.reset()
for k in range(100):
await RisingEdge(dut.clk)
tb.dut.cfg_tx_enable.value = 1
test_frames = [payload_data(x) for x in payload_lengths()]
total_bytes = 0
total_pkts = 0
for test_data in test_frames:
await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
total_bytes += max(len(test_data), 60)+4
total_pkts += 1
for test_data in test_frames:
rx_frame = await tb.sink.recv()
tx_cpl = await tb.tx_cpl_sink.recv()
ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= tb.clk_period/2*2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
assert tb.sink.empty()
for stat, val in tb.stats.items():
tb.log.info("%s: %d", stat, val)
assert tb.stats["stat_tx_byte"] == total_bytes
assert tb.stats["stat_tx_pkt_len"] == total_bytes
assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
assert tb.stats["stat_tx_pkt_mcast"] == 0
assert tb.stats["stat_tx_pkt_bcast"] == 0
assert tb.stats["stat_tx_pkt_vlan"] == 0
assert tb.stats["stat_tx_pkt_good"] == total_pkts
assert tb.stats["stat_tx_pkt_bad"] == 0
assert tb.stats["stat_tx_err_oversize"] == 0
assert tb.stats["stat_tx_err_user"] == 0
assert tb.stats["stat_tx_err_underflow"] == 0
for k in range(10):
await RisingEdge(dut.clk)
async def run_test_underrun(dut, gbx_cfg=None, ifg=12):
tb = TB(dut, gbx_cfg)
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
await tb.reset()
for k in range(100):
await RisingEdge(dut.clk)
tb.dut.cfg_tx_enable.value = 1
test_data = bytes(x for x in range(60))
for k in range(3):
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(32):
await RisingEdge(dut.clk)
tb.source.pause = True
for k in range(4):
await RisingEdge(dut.clk)
tb.source.pause = False
for k in range(3):
rx_frame = await tb.sink.recv()
if k == 1:
assert rx_frame.data[-1] == 0xFE
assert rx_frame.ctrl[-1] == 1
else:
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert tb.sink.empty()
for stat, val in tb.stats.items():
tb.log.info("%s: %d", stat, val)
assert tb.stats["stat_tx_byte"] > 64*2 + 32
assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
assert tb.stats["stat_tx_pkt_ucast"] == 3
assert tb.stats["stat_tx_pkt_mcast"] == 0
assert tb.stats["stat_tx_pkt_bcast"] == 0
assert tb.stats["stat_tx_pkt_vlan"] == 0
assert tb.stats["stat_tx_pkt_good"] == 2
assert tb.stats["stat_tx_pkt_bad"] == 1
assert tb.stats["stat_tx_err_oversize"] == 0
assert tb.stats["stat_tx_err_user"] == 0
assert tb.stats["stat_tx_err_underflow"] == 1
for k in range(10):
await RisingEdge(dut.clk)
async def run_test_error(dut, gbx_cfg=None, ifg=12):
tb = TB(dut, gbx_cfg)
tb.dut.cfg_tx_max_pkt_len.value = 9218
tb.dut.cfg_tx_ifg.value = ifg
await tb.reset()
for k in range(100):
await RisingEdge(dut.clk)
tb.dut.cfg_tx_enable.value = 1
test_data = bytes(x for x in range(60))
for k in range(3):
test_frame = AxiStreamFrame(test_data)
if k == 1:
test_frame.tuser = 1
await tb.source.send(test_frame)
for k in range(3):
rx_frame = await tb.sink.recv()
if k == 1:
assert rx_frame.data[-1] == 0xFE
assert rx_frame.ctrl[-1] == 1
else:
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert tb.sink.empty()
for stat, val in tb.stats.items():
tb.log.info("%s: %d", stat, val)
assert tb.stats["stat_tx_byte"] > 64*2 + 32
assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
assert tb.stats["stat_tx_pkt_ucast"] == 3
assert tb.stats["stat_tx_pkt_mcast"] == 0
assert tb.stats["stat_tx_pkt_bcast"] == 0
assert tb.stats["stat_tx_pkt_vlan"] == 0
assert tb.stats["stat_tx_pkt_good"] == 2
assert tb.stats["stat_tx_pkt_bad"] == 1
assert tb.stats["stat_tx_err_oversize"] == 0
assert tb.stats["stat_tx_err_user"] == 1
assert tb.stats["stat_tx_err_underflow"] == 0
for k in range(10):
await RisingEdge(dut.clk)
async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
tb = TB(dut, gbx_cfg)
tb.dut.cfg_tx_max_pkt_len.value = 1518
tb.dut.cfg_tx_ifg.value = ifg
await tb.reset()
for k in range(100):
await RisingEdge(dut.clk)
tb.dut.cfg_tx_enable.value = 1
for max_len in range(128-4-8, 128-4+9):
tb.stats_reset()
total_bytes = 0
total_pkts = 0
good_bytes = 0
oversz_pkts = 0
oversz_bytes_in = 0
oversz_bytes_out = 0
for test_pkt_len in range(max_len-8, max_len+9):
tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
tb.dut.cfg_tx_max_pkt_len.value = max_len+4
test_data_1 = bytes(x for x in range(60))
test_data_2 = bytes(x for x in range(test_pkt_len))
for k in range(3):
if k == 1:
test_data = test_data_2
else:
test_data = test_data_1
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
total_bytes += max(len(test_data), 60)+4
total_pkts += 1
if len(test_data) > max_len:
oversz_pkts += 1
oversz_bytes_in += len(test_data)+4
oversz_bytes_out += max_len
else:
good_bytes += len(test_data)+4
for k in range(3):
rx_frame = await tb.sink.recv()
if k == 1:
if test_pkt_len > max_len:
assert rx_frame.data[-1] == 0xFE
assert rx_frame.ctrl[-1] == 1
else:
assert rx_frame.get_payload() == test_data_2
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
else:
assert rx_frame.get_payload() == test_data_1
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert tb.sink.empty()
for stat, val in tb.stats.items():
tb.log.info("%s: %d", stat, val)
assert tb.stats["stat_tx_byte"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
assert tb.stats["stat_tx_byte"] <= good_bytes+oversz_bytes_in
assert tb.stats["stat_tx_pkt_len"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
assert tb.stats["stat_tx_pkt_len"] <= good_bytes+oversz_bytes_in
assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
assert tb.stats["stat_tx_pkt_mcast"] == 0
assert tb.stats["stat_tx_pkt_bcast"] == 0
assert tb.stats["stat_tx_pkt_vlan"] == 0
assert tb.stats["stat_tx_pkt_good"] == total_pkts - oversz_pkts
assert tb.stats["stat_tx_pkt_bad"] == oversz_pkts
assert tb.stats["stat_tx_err_oversize"] == oversz_pkts
assert tb.stats["stat_tx_err_user"] == 0
assert tb.stats["stat_tx_err_underflow"] == 0
for k in range(10):
await RisingEdge(dut.clk)
def size_list():
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def cycle_en():
return itertools.cycle([0, 0, 0, 1])
if cocotb.SIM_NAME:
gbx_cfgs = [None]
if cocotb.top.GBX_IF_EN.value:
gbx_cfgs.append((33, [32]))
gbx_cfgs.append((66, [64, 65]))
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12])
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
for test in [
run_test_underrun,
run_test_error,
run_test_oversize
]:
factory = TestFactory(test)
factory.add_option("ifg", [12])
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("dic_en", [1, 0])
@pytest.mark.parametrize("gbx_en", [1, 0])
def test_taxi_axis_baser_tx_32(request, gbx_en, dic_en):
dut = "taxi_axis_baser_tx_32"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = 32
parameters['HDR_W'] = 2
parameters['GBX_IF_EN'] = gbx_en
parameters['GBX_CNT'] = 1
parameters['PADDING_EN'] = 1
parameters['DIC_EN'] = dic_en
parameters['MIN_FRAME_LEN'] = 64
parameters['PTP_TS_EN'] = 1
parameters['PTP_TS_FMT_TOD'] = 1
parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
parameters['TX_TAG_W'] = 16
parameters['TX_CPL_CTRL_IN_TUSER'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

135
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream 10GBASE-R frame transmitter testbench
*/
module test_taxi_axis_baser_tx_32 #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter GBX_CNT = 1,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,
parameter logic PTP_TS_FMT_TOD = 1'b1,
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_TAG_W = 16,
parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0
/* verilator lint_on WIDTHTRUNC */
)
();
localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
logic clk;
logic rst;
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
logic [DATA_W-1:0] encoded_tx_data;
logic encoded_tx_data_valid;
logic [HDR_W-1:0] encoded_tx_hdr;
logic encoded_tx_hdr_valid;
logic [GBX_CNT-1:0] tx_gbx_req_sync;
logic tx_gbx_req_stall;
logic [GBX_CNT-1:0] tx_gbx_sync;
logic [PTP_TS_W-1:0] ptp_ts;
logic [15:0] cfg_tx_max_pkt_len;
logic [7:0] cfg_tx_ifg;
logic cfg_tx_enable;
logic tx_start_packet;
logic [2:0] stat_tx_byte;
logic [15:0] stat_tx_pkt_len;
logic stat_tx_pkt_ucast;
logic stat_tx_pkt_mcast;
logic stat_tx_pkt_bcast;
logic stat_tx_pkt_vlan;
logic stat_tx_pkt_good;
logic stat_tx_pkt_bad;
logic stat_tx_err_oversize;
logic stat_tx_err_user;
logic stat_tx_err_underflow;
taxi_axis_baser_tx_32 #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_W(PTP_TS_W),
.TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis_tx(s_axis_tx),
.m_axis_tx_cpl(m_axis_tx_cpl),
/*
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_sync(tx_gbx_req_sync),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_sync(tx_gbx_sync),
/*
* PTP
*/
.ptp_ts(ptp_ts),
/*
* Configuration
*/
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
.cfg_tx_ifg(cfg_tx_ifg),
.cfg_tx_enable(cfg_tx_enable),
/*
* Status
*/
.tx_start_packet(tx_start_packet),
.stat_tx_byte(stat_tx_byte),
.stat_tx_pkt_len(stat_tx_pkt_len),
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
.stat_tx_pkt_good(stat_tx_pkt_good),
.stat_tx_pkt_bad(stat_tx_pkt_bad),
.stat_tx_err_oversize(stat_tx_err_oversize),
.stat_tx_err_user(stat_tx_err_user),
.stat_tx_err_underflow(stat_tx_err_underflow)
);
endmodule
`resetall