eth: Add 32-bit AXI stream BASE-R TX module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/tb/taxi_axis_baser_tx_32/Makefile

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_baser_tx_32
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_HDR_W := 2
+export PARAM_GBX_IF_EN := 1
+export PARAM_GBX_CNT := 1
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_TX_CPL_CTRL_IN_TUSER := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_baser_tx_32/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.py

@@ -0,0 +1,491 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+try:
+    from baser import BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut, gbx_cfg=None):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if gbx_cfg:
+            self.clk_period = 3.102
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.clk, self.clk_period, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
+        self.sink = BaseRSerdesSink(
+            data=dut.encoded_tx_data,
+            data_valid=dut.encoded_tx_data_valid,
+            hdr=dut.encoded_tx_hdr,
+            hdr_valid=dut.encoded_tx_hdr_valid,
+            gbx_req_sync=dut.tx_gbx_req_sync,
+            gbx_req_stall=dut.tx_gbx_req_stall,
+            gbx_sync=dut.tx_gbx_sync,
+            clock=dut.clk,
+            scramble=False,
+            gbx_cfg=gbx_cfg
+        )
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["stat_tx_byte"] = 0
+        self.stats["stat_tx_pkt_len"] = 0
+        self.stats["stat_tx_pkt_ucast"] = 0
+        self.stats["stat_tx_pkt_mcast"] = 0
+        self.stats["stat_tx_pkt_bcast"] = 0
+        self.stats["stat_tx_pkt_vlan"] = 0
+        self.stats["stat_tx_pkt_good"] = 0
+        self.stats["stat_tx_pkt_bad"] = 0
+        self.stats["stat_tx_err_oversize"] = 0
+        self.stats["stat_tx_err_user"] = 0
+        self.stats["stat_tx_err_underflow"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut, gbx_cfg)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.clk)
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= tb.clk_period/2*2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        if gbx_cfg is None:
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    for k in range(10):
+        await RisingEdge(dut.clk)
+
+
+async def run_test_underrun(dut, gbx_cfg=None, ifg=12):
+
+    tb = TB(dut, gbx_cfg)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.clk)
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.source.send(test_frame)
+
+    for k in range(32):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 1
+
+    for k in range(10):
+        await RisingEdge(dut.clk)
+
+
+async def run_test_error(dut, gbx_cfg=None, ifg=12):
+
+    tb = TB(dut, gbx_cfg)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.clk)
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 1
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    for k in range(10):
+        await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
+
+    tb = TB(dut, gbx_cfg)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.clk)
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_tx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = AxiStreamFrame(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        assert rx_frame.data[-1] == 0xFE
+                        assert rx_frame.ctrl[-1] == 1
+                    else:
+                        assert rx_frame.get_payload() == test_data_2
+                        assert rx_frame.check_fcs()
+                        assert rx_frame.ctrl is None
+                else:
+                    assert rx_frame.get_payload() == test_data_1
+                    assert rx_frame.check_fcs()
+                    assert rx_frame.ctrl is None
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["stat_tx_byte"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_len"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_tx_pkt_mcast"] == 0
+        assert tb.stats["stat_tx_pkt_bcast"] == 0
+        assert tb.stats["stat_tx_pkt_vlan"] == 0
+        assert tb.stats["stat_tx_pkt_good"] == total_pkts - oversz_pkts
+        assert tb.stats["stat_tx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_tx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_tx_err_user"] == 0
+        assert tb.stats["stat_tx_err_underflow"] == 0
+
+    for k in range(10):
+        await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    gbx_cfgs = [None]
+
+    if cocotb.top.GBX_IF_EN.value:
+        gbx_cfgs.append((33, [32]))
+        gbx_cfgs.append((66, [64, 65]))
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.add_option("gbx_cfg", gbx_cfgs)
+    factory.generate_tests()
+
+    for test in [
+                run_test_underrun,
+                run_test_error,
+                run_test_oversize
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.add_option("gbx_cfg", gbx_cfgs)
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("dic_en", [1, 0])
+@pytest.mark.parametrize("gbx_en", [1, 0])
+def test_taxi_axis_baser_tx_32(request, gbx_en, dic_en):
+    dut = "taxi_axis_baser_tx_32"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 32
+    parameters['HDR_W'] = 2
+    parameters['GBX_IF_EN'] = gbx_en
+    parameters['GBX_CNT'] = 1
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['TX_CPL_CTRL_IN_TUSER'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.sv

@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream 10GBASE-R frame transmitter testbench
+ */
+module test_taxi_axis_baser_tx_32 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter HDR_W = 2,
+    parameter logic GBX_IF_EN = 1'b0,
+    parameter GBX_CNT = 1,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+
+logic [DATA_W-1:0] encoded_tx_data;
+logic encoded_tx_data_valid;
+logic [HDR_W-1:0] encoded_tx_hdr;
+logic encoded_tx_hdr_valid;
+logic [GBX_CNT-1:0] tx_gbx_req_sync;
+logic tx_gbx_req_stall;
+logic [GBX_CNT-1:0] tx_gbx_sync;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+
+logic tx_start_packet;
+logic [2:0] stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+
+taxi_axis_baser_tx_32 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .GBX_IF_EN(GBX_IF_EN),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * 10GBASE-R encoded interface
+     */
+    .encoded_tx_data(encoded_tx_data),
+    .encoded_tx_data_valid(encoded_tx_data_valid),
+    .encoded_tx_hdr(encoded_tx_hdr),
+    .encoded_tx_hdr_valid(encoded_tx_hdr_valid),
+    .tx_gbx_req_sync(tx_gbx_req_sync),
+    .tx_gbx_req_stall(tx_gbx_req_stall),
+    .tx_gbx_sync(tx_gbx_sync),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow)
+);
+
+endmodule
+
+`resetall