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axi: Minor cleanup in AXIL-APB adapter module

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-11-12 17:04:59 -08:00
parent 18794f33c9
commit ee31bbf936
1 changed files with 4 additions and 4 deletions
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8
src/axi/rtl/taxi_axil_apb_adapter.sv
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@@ -73,7 +73,7 @@ if (AXIL_BYTE_W * AXIL_STRB_W != AXIL_DATA_W)
$fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)"); $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
if (APB_BYTE_W * APB_STRB_W != APB_DATA_W) if (APB_BYTE_W * APB_STRB_W != APB_DATA_W)
$fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)"); $fatal(0, "Error: APB master interface data width not evenly divisible (instance %m)");
if (AXIL_BYTE_W != APB_BYTE_W) if (AXIL_BYTE_W != APB_BYTE_W)
$fatal(0, "Error: byte size mismatch (instance %m)"); $fatal(0, "Error: byte size mismatch (instance %m)");
@@ -287,7 +287,7 @@ if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
s_axil_rvalid_reg <= 1'b0; s_axil_rvalid_reg <= 1'b0;
m_apb_psel_reg <= 1'b0; m_apb_psel_reg <= 1'b0;
m_apb_penable_reg <= 1'b0; m_apb_penable_reg <= 1'b0;
end end
end end
@@ -486,7 +486,7 @@ end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
s_axil_rvalid_reg <= 1'b0; s_axil_rvalid_reg <= 1'b0;
m_apb_psel_reg <= 1'b0; m_apb_psel_reg <= 1'b0;
m_apb_penable_reg <= 1'b0; m_apb_penable_reg <= 1'b0;
end end
end end
@@ -726,7 +726,7 @@ end else begin : downsize
s_axil_rvalid_reg <= 1'b0; s_axil_rvalid_reg <= 1'b0;
m_apb_psel_reg <= 1'b0; m_apb_psel_reg <= 1'b0;
m_apb_penable_reg <= 1'b0; m_apb_penable_reg <= 1'b0;
end end
end end