mirror of
https://github.com/fpganinja/taxi.git
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lss: Add I2C single register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -85,6 +85,7 @@ To facilitate the dual-license model, contributions to the project can only be a
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* LFSR self-synchronizing descrambler
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* Low-speed serial
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* I2C master
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* I2C single register
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* MDIO master
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* UART
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* Primitives
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252
rtl/lss/taxi_i2c_single_reg.sv
Normal file
252
rtl/lss/taxi_i2c_single_reg.sv
Normal file
@@ -0,0 +1,252 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2023-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* I2C single register
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*/
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module taxi_i2c_single_reg #(
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parameter FILTER_LEN = 4,
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parameter logic [6:0] DEV_ADDR = 7'h70
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* I2C interface
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*/
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input wire logic scl_i,
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output wire logic scl_o,
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output wire logic scl_t,
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input wire logic sda_i,
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output wire logic sda_o,
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output wire logic sda_t,
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/*
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* Data register
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*/
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input wire logic [7:0] data_in = '0,
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input wire logic data_latch = '0,
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output wire logic [7:0] data_out
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);
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_ADDRESS = 3'd1,
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STATE_ACK = 3'd2,
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STATE_WRITE_1 = 3'd3,
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STATE_WRITE_2 = 3'd4,
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STATE_READ_1 = 3'd5,
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STATE_READ_2 = 3'd6,
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STATE_READ_3 = 3'd7;
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logic [2:0] state_reg = STATE_IDLE;
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logic [7:0] data_reg = '0;
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logic [7:0] shift_reg = '0;
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logic mode_read_reg = 1'b0;
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logic [3:0] bit_count_reg = '0;
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logic [FILTER_LEN-1:0] scl_i_filter_reg = '1;
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logic [FILTER_LEN-1:0] sda_i_filter_reg = '1;
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logic scl_i_reg = 1'b1;
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logic sda_i_reg = 1'b1;
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logic sda_o_reg = 1'b1;
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logic last_scl_i_reg = 1'b1;
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logic last_sda_i_reg = 1'b1;
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assign scl_o = 1'b1;
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assign scl_t = 1'b1;
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assign sda_o = sda_o_reg;
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assign sda_t = sda_o_reg;
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assign data_out = data_reg;
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wire scl_posedge = scl_i_reg && !last_scl_i_reg;
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wire scl_negedge = !scl_i_reg && last_scl_i_reg;
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wire sda_posedge = sda_i_reg && !last_sda_i_reg;
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wire sda_negedge = !sda_i_reg && last_sda_i_reg;
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wire start_bit = sda_negedge && scl_i_reg;
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wire stop_bit = sda_posedge && scl_i_reg;
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always_ff @(posedge clk) begin
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if (start_bit) begin
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sda_o_reg <= 1'b1;
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bit_count_reg <= 4'd7;
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state_reg <= STATE_ADDRESS;
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end else if (stop_bit) begin
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sda_o_reg <= 1'b1;
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state_reg <= STATE_IDLE;
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end else begin
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case (state_reg)
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STATE_IDLE: begin
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// line idle
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sda_o_reg <= 1'b1;
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state_reg <= STATE_IDLE;
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end
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STATE_ADDRESS: begin
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// read address
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sda_o_reg <= 1'b1;
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if (scl_posedge) begin
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if (bit_count_reg > 0) begin
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// shift in address
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bit_count_reg <= bit_count_reg-1;
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shift_reg <= {shift_reg[6:0], sda_i_reg};
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state_reg <= STATE_ADDRESS;
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end else begin
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// check address
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mode_read_reg <= sda_i_reg;
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if (shift_reg[6:0] == DEV_ADDR) begin
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// it's a match, send ACK
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state_reg <= STATE_ACK;
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end else begin
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// no match, return to idle
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state_reg <= STATE_IDLE;
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end
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end
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end else begin
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state_reg <= STATE_ADDRESS;
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end
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end
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STATE_ACK: begin
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// send ACK bit
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if (scl_negedge) begin
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sda_o_reg <= 1'b0;
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bit_count_reg <= 4'd7;
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if (mode_read_reg) begin
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// reading
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shift_reg <= data_reg;
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state_reg <= STATE_READ_1;
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end else begin
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// writing
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state_reg <= STATE_WRITE_1;
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end
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end else begin
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state_reg <= STATE_ACK;
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end
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end
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STATE_WRITE_1: begin
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// write data byte
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if (scl_negedge) begin
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sda_o_reg <= 1'b1;
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state_reg <= STATE_WRITE_2;
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end else begin
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state_reg <= STATE_WRITE_1;
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end
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end
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STATE_WRITE_2: begin
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// write data byte
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sda_o_reg <= 1'b1;
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if (scl_posedge) begin
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// shift in data bit
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shift_reg <= {shift_reg[6:0], sda_i_reg};
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if (bit_count_reg > 0) begin
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bit_count_reg <= bit_count_reg-1;
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state_reg <= STATE_WRITE_2;
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end else begin
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data_reg <= {shift_reg[6:0], sda_i_reg};
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state_reg <= STATE_ACK;
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end
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end else begin
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state_reg <= STATE_WRITE_2;
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end
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end
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STATE_READ_1: begin
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// read data byte
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if (scl_negedge) begin
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// shift out data bit
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{sda_o_reg, shift_reg} <= {shift_reg, sda_i_reg};
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if (bit_count_reg > 0) begin
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bit_count_reg <= bit_count_reg-1;
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state_reg <= STATE_READ_1;
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end else begin
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state_reg <= STATE_READ_2;
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end
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end else begin
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state_reg <= STATE_READ_1;
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end
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end
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STATE_READ_2: begin
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// read ACK bit
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if (scl_negedge) begin
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// release SDA
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sda_o_reg <= 1'b1;
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state_reg <= STATE_READ_3;
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end else begin
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state_reg <= STATE_READ_2;
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end
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end
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STATE_READ_3: begin
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// read ACK bit
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if (scl_posedge) begin
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if (sda_i_reg) begin
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// NACK, return to idle
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state_reg <= STATE_IDLE;
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end else begin
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// ACK, read another byte
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bit_count_reg <= 4'd7;
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shift_reg <= data_reg;
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state_reg <= STATE_READ_1;
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end
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end else begin
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state_reg <= STATE_READ_3;
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end
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end
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endcase
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end
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if (data_latch) begin
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data_reg <= data_in;
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end
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scl_i_filter_reg <= {scl_i_filter_reg[FILTER_LEN-2:0], scl_i};
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sda_i_filter_reg <= {sda_i_filter_reg[FILTER_LEN-2:0], sda_i};
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if (scl_i_filter_reg == '1) begin
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scl_i_reg <= 1'b1;
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end else if (scl_i_filter_reg == '0) begin
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scl_i_reg <= 1'b0;
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end
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if (sda_i_filter_reg == '1) begin
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sda_i_reg <= 1'b1;
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end else if (sda_i_filter_reg == '0) begin
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sda_i_reg <= 1'b0;
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end
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last_scl_i_reg <= scl_i_reg;
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last_sda_i_reg <= sda_i_reg;
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if (rst) begin
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state_reg <= STATE_IDLE;
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data_reg <= 8'd0;
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sda_o_reg <= 1'b1;
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end
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end
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endmodule
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`resetall
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47
tb/lss/taxi_i2c_single_reg/Makefile
Normal file
47
tb/lss/taxi_i2c_single_reg/Makefile
Normal file
@@ -0,0 +1,47 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2023-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ns
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DUT = taxi_i2c_single_reg
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_FILTER_LEN := 4
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export PARAM_DEV_ADDR := $(shell echo $$((0x70)) )
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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152
tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py
Normal file
152
tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py
Normal file
@@ -0,0 +1,152 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2023-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.i2c import I2cMaster
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.fork(Clock(dut.clk, 8, units="ns").start())
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self.i2c_master = I2cMaster(sda=dut.sda_o, sda_o=dut.sda_i,
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scl=dut.scl_o, scl_o=dut.scl_i, speed=4000e3)
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dut.data_in.setimmediatevalue(0)
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dut.data_latch.setimmediatevalue(0)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None):
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tb = TB(dut)
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await tb.reset()
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tb.log.info("Test write")
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await tb.i2c_master.write(0x70, b'\x11\xAA')
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await tb.i2c_master.send_stop()
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assert dut.data_out.value.integer == 0xAA
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tb.log.info("Test zero-length write")
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await tb.i2c_master.write(0x70, b'')
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await tb.i2c_master.send_stop()
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assert dut.data_out.value.integer == 0xAA
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tb.log.info("Test read")
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await RisingEdge(dut.clk)
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dut.data_in.value = 0x55
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dut.data_latch.value = 1
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await RisingEdge(dut.clk)
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dut.data_latch.value = 0
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data = await tb.i2c_master.read(0x70, 4)
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await tb.i2c_master.send_stop()
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tb.log.info("Read data: %s", data)
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assert data == b'\x55'*4
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tb.log.info("Test write to nonexistent device")
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await tb.i2c_master.write(0x55, b'\x00\x04'+b'\xde\xad\xbe\xef')
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await tb.i2c_master.send_stop()
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# assert missed ack
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test)
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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def test_taxi_i2c_single_reg(request):
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dut = "taxi_i2c_single_reg"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, "lss", f"{dut}.sv"),
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]
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parameters = {}
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parameters['FILTER_LEN'] = 4
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parameters['DEV_ADDR'] = 0x70
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
|
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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69
tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv
Normal file
69
tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv
Normal file
@@ -0,0 +1,69 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* I2C single register testbench
|
||||
*/
|
||||
module test_taxi_i2c_single_reg #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter FILTER_LEN = 4,
|
||||
parameter logic [6:0] DEV_ADDR = 7'h70
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
logic scl_i;
|
||||
logic scl_o;
|
||||
logic scl_t;
|
||||
logic sda_i;
|
||||
logic sda_o;
|
||||
logic sda_t;
|
||||
|
||||
logic [7:0] data_in;
|
||||
logic data_latch;
|
||||
logic [7:0] data_out;
|
||||
|
||||
taxi_i2c_single_reg #(
|
||||
.FILTER_LEN(FILTER_LEN),
|
||||
.DEV_ADDR(DEV_ADDR)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* I2C interface
|
||||
*/
|
||||
.scl_i(scl_i),
|
||||
.scl_o(scl_o),
|
||||
.scl_t(scl_t),
|
||||
.sda_i(sda_i),
|
||||
.sda_o(sda_o),
|
||||
.sda_t(sda_t),
|
||||
|
||||
/*
|
||||
* Data register
|
||||
*/
|
||||
.data_in(data_in),
|
||||
.data_latch(data_latch),
|
||||
.data_out(data_out)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user