lss: Add I2C single register module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/lss/taxi_i2c_single_reg/Makefile

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ns
+
+DUT      = taxi_i2c_single_reg
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_FILTER_LEN := 4
+export PARAM_DEV_ADDR := $(shell echo $$((0x70)) )
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py

@@ -0,0 +1,152 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.i2c import I2cMaster
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.fork(Clock(dut.clk, 8, units="ns").start())
+
+        self.i2c_master = I2cMaster(sda=dut.sda_o, sda_o=dut.sda_i,
+            scl=dut.scl_o, scl_o=dut.scl_i, speed=4000e3)
+
+        dut.data_in.setimmediatevalue(0)
+        dut.data_latch.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.log.info("Test write")
+
+    await tb.i2c_master.write(0x70, b'\x11\xAA')
+    await tb.i2c_master.send_stop()
+
+    assert dut.data_out.value.integer == 0xAA
+
+    tb.log.info("Test zero-length write")
+
+    await tb.i2c_master.write(0x70, b'')
+    await tb.i2c_master.send_stop()
+
+    assert dut.data_out.value.integer == 0xAA
+
+    tb.log.info("Test read")
+
+    await RisingEdge(dut.clk)
+    dut.data_in.value = 0x55
+    dut.data_latch.value = 1
+    await RisingEdge(dut.clk)
+    dut.data_latch.value = 0
+
+    data = await tb.i2c_master.read(0x70, 4)
+    await tb.i2c_master.send_stop()
+
+    tb.log.info("Read data: %s", data)
+
+    assert data == b'\x55'*4
+
+    tb.log.info("Test write to nonexistent device")
+
+    await tb.i2c_master.write(0x55, b'\x00\x04'+b'\xde\xad\xbe\xef')
+    await tb.i2c_master.send_stop()
+
+    # assert missed ack
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_i2c_single_reg(request):
+    dut = "taxi_i2c_single_reg"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "lss", f"{dut}.sv"),
+    ]
+
+    parameters = {}
+
+    parameters['FILTER_LEN'] = 4
+    parameters['DEV_ADDR'] = 0x70
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv

@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C single register testbench
+ */
+module test_taxi_i2c_single_reg #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter FILTER_LEN = 4,
+    parameter logic [6:0] DEV_ADDR = 7'h70
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+logic scl_i;
+logic scl_o;
+logic scl_t;
+logic sda_i;
+logic sda_o;
+logic sda_t;
+
+logic [7:0] data_in;
+logic data_latch;
+logic [7:0] data_out;
+
+taxi_i2c_single_reg #(
+    .FILTER_LEN(FILTER_LEN),
+    .DEV_ADDR(DEV_ADDR)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(scl_i),
+    .scl_o(scl_o),
+    .scl_t(scl_t),
+    .sda_i(sda_i),
+    .sda_o(sda_o),
+    .sda_t(sda_t),
+
+    /*
+     * Data register
+     */
+    .data_in(data_in),
+    .data_latch(data_latch),
+    .data_out(data_out)
+);
+
+endmodule
+
+`resetall