lss: Add I2C single register module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

README.md

@@ -85,6 +85,7 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  LFSR self-synchronizing descrambler
 *  Low-speed serial
     *  I2C master
+    *  I2C single register
     *  MDIO master
     *  UART
 *  Primitives

rtl/lss/taxi_i2c_single_reg.sv

@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C single register
+ */
+module taxi_i2c_single_reg #(
+    parameter FILTER_LEN = 4,
+    parameter logic [6:0] DEV_ADDR = 7'h70
+)
+(
+    input  wire logic        clk,
+    input  wire logic        rst,
+
+    /*
+     * I2C interface
+     */
+    input  wire logic        scl_i,
+    output wire logic        scl_o,
+    output wire logic        scl_t,
+    input  wire logic        sda_i,
+    output wire logic        sda_o,
+    output wire logic        sda_t,
+
+    /*
+     * Data register
+     */
+    input  wire logic [7:0]  data_in = '0,
+    input  wire logic        data_latch = '0,
+    output wire logic [7:0]  data_out
+);
+
+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_ADDRESS = 3'd1,
+    STATE_ACK = 3'd2,
+    STATE_WRITE_1 = 3'd3,
+    STATE_WRITE_2 = 3'd4,
+    STATE_READ_1 = 3'd5,
+    STATE_READ_2 = 3'd6,
+    STATE_READ_3 = 3'd7;
+
+logic [2:0] state_reg = STATE_IDLE;
+
+logic [7:0] data_reg = '0;
+logic [7:0] shift_reg = '0;
+
+logic mode_read_reg = 1'b0;
+
+logic [3:0] bit_count_reg = '0;
+
+logic [FILTER_LEN-1:0] scl_i_filter_reg = '1;
+logic [FILTER_LEN-1:0] sda_i_filter_reg = '1;
+
+logic scl_i_reg = 1'b1;
+logic sda_i_reg = 1'b1;
+
+logic sda_o_reg = 1'b1;
+
+logic last_scl_i_reg = 1'b1;
+logic last_sda_i_reg = 1'b1;
+
+assign scl_o = 1'b1;
+assign scl_t = 1'b1;
+assign sda_o = sda_o_reg;
+assign sda_t = sda_o_reg;
+
+assign data_out = data_reg;
+
+wire scl_posedge = scl_i_reg && !last_scl_i_reg;
+wire scl_negedge = !scl_i_reg && last_scl_i_reg;
+wire sda_posedge = sda_i_reg && !last_sda_i_reg;
+wire sda_negedge = !sda_i_reg && last_sda_i_reg;
+
+wire start_bit = sda_negedge && scl_i_reg;
+wire stop_bit = sda_posedge && scl_i_reg;
+
+always_ff @(posedge clk) begin
+
+    if (start_bit) begin
+        sda_o_reg <= 1'b1;
+
+        bit_count_reg <= 4'd7;
+        state_reg <= STATE_ADDRESS;
+    end else if (stop_bit) begin
+        sda_o_reg <= 1'b1;
+
+        state_reg <= STATE_IDLE;
+    end else begin
+        case (state_reg)
+            STATE_IDLE: begin
+                // line idle
+                sda_o_reg <= 1'b1;
+
+                state_reg <= STATE_IDLE;
+            end
+            STATE_ADDRESS: begin
+                // read address
+                sda_o_reg <= 1'b1;
+
+                if (scl_posedge) begin
+                    if (bit_count_reg > 0) begin
+                        // shift in address
+                        bit_count_reg <= bit_count_reg-1;
+                        shift_reg <= {shift_reg[6:0], sda_i_reg};
+                        state_reg <= STATE_ADDRESS;
+                    end else begin
+                        // check address
+                        mode_read_reg <= sda_i_reg;
+                        if (shift_reg[6:0] == DEV_ADDR) begin
+                            // it's a match, send ACK
+                            state_reg <= STATE_ACK;
+                        end else begin
+                            // no match, return to idle
+                            state_reg <= STATE_IDLE;
+                        end
+                    end
+                end else begin
+                    state_reg <= STATE_ADDRESS;
+                end
+            end
+            STATE_ACK: begin
+                // send ACK bit
+                if (scl_negedge) begin
+                    sda_o_reg <= 1'b0;
+                    bit_count_reg <= 4'd7;
+                    if (mode_read_reg) begin
+                        // reading
+                        shift_reg <= data_reg;
+                        state_reg <= STATE_READ_1;
+                    end else begin
+                        // writing
+                        state_reg <= STATE_WRITE_1;
+                    end
+                end else begin
+                    state_reg <= STATE_ACK;
+                end
+            end
+            STATE_WRITE_1: begin
+                // write data byte
+                if (scl_negedge) begin
+                    sda_o_reg <= 1'b1;
+                    state_reg <= STATE_WRITE_2;
+                end else begin
+                    state_reg <= STATE_WRITE_1;
+                end
+            end
+            STATE_WRITE_2: begin
+                // write data byte
+                sda_o_reg <= 1'b1;
+                if (scl_posedge) begin
+                    // shift in data bit
+                    shift_reg <= {shift_reg[6:0], sda_i_reg};
+                    if (bit_count_reg > 0) begin
+                        bit_count_reg <= bit_count_reg-1;
+                        state_reg <= STATE_WRITE_2;
+                    end else begin
+                        data_reg <= {shift_reg[6:0], sda_i_reg};
+                        state_reg <= STATE_ACK;
+                    end
+                end else begin
+                    state_reg <= STATE_WRITE_2;
+                end
+            end
+            STATE_READ_1: begin
+                // read data byte
+                if (scl_negedge) begin
+                    // shift out data bit
+                    {sda_o_reg, shift_reg} <= {shift_reg, sda_i_reg};
+
+                    if (bit_count_reg > 0) begin
+                        bit_count_reg <= bit_count_reg-1;
+                        state_reg <= STATE_READ_1;
+                    end else begin
+                        state_reg <= STATE_READ_2;
+                    end
+                end else begin
+                    state_reg <= STATE_READ_1;
+                end
+            end
+            STATE_READ_2: begin
+                // read ACK bit
+                if (scl_negedge) begin
+                    // release SDA
+                    sda_o_reg <= 1'b1;
+                    state_reg <= STATE_READ_3;
+                end else begin
+                    state_reg <= STATE_READ_2;
+                end
+            end
+            STATE_READ_3: begin
+                // read ACK bit
+                if (scl_posedge) begin
+                    if (sda_i_reg) begin
+                        // NACK, return to idle
+                        state_reg <= STATE_IDLE;
+                    end else begin
+                        // ACK, read another byte
+                        bit_count_reg <= 4'd7;
+                        shift_reg <= data_reg;
+                        state_reg <= STATE_READ_1;
+                    end
+                end else begin
+                    state_reg <= STATE_READ_3;
+                end
+            end
+        endcase
+    end
+
+    if (data_latch) begin
+        data_reg <= data_in;
+    end
+
+    scl_i_filter_reg <= {scl_i_filter_reg[FILTER_LEN-2:0], scl_i};
+    sda_i_filter_reg <= {sda_i_filter_reg[FILTER_LEN-2:0], sda_i};
+
+    if (scl_i_filter_reg == '1) begin
+        scl_i_reg <= 1'b1;
+    end else if (scl_i_filter_reg == '0) begin
+        scl_i_reg <= 1'b0;
+    end
+
+    if (sda_i_filter_reg == '1) begin
+        sda_i_reg <= 1'b1;
+    end else if (sda_i_filter_reg == '0) begin
+        sda_i_reg <= 1'b0;
+    end
+
+    last_scl_i_reg <= scl_i_reg;
+    last_sda_i_reg <= sda_i_reg;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        data_reg <= 8'd0;
+        sda_o_reg <= 1'b1;
+    end
+end
+
+endmodule
+
+`resetall

tb/lss/taxi_i2c_single_reg/Makefile

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ns
+
+DUT      = taxi_i2c_single_reg
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_FILTER_LEN := 4
+export PARAM_DEV_ADDR := $(shell echo $$((0x70)) )
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.py

@@ -0,0 +1,152 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.i2c import I2cMaster
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.fork(Clock(dut.clk, 8, units="ns").start())
+
+        self.i2c_master = I2cMaster(sda=dut.sda_o, sda_o=dut.sda_i,
+            scl=dut.scl_o, scl_o=dut.scl_i, speed=4000e3)
+
+        dut.data_in.setimmediatevalue(0)
+        dut.data_latch.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.log.info("Test write")
+
+    await tb.i2c_master.write(0x70, b'\x11\xAA')
+    await tb.i2c_master.send_stop()
+
+    assert dut.data_out.value.integer == 0xAA
+
+    tb.log.info("Test zero-length write")
+
+    await tb.i2c_master.write(0x70, b'')
+    await tb.i2c_master.send_stop()
+
+    assert dut.data_out.value.integer == 0xAA
+
+    tb.log.info("Test read")
+
+    await RisingEdge(dut.clk)
+    dut.data_in.value = 0x55
+    dut.data_latch.value = 1
+    await RisingEdge(dut.clk)
+    dut.data_latch.value = 0
+
+    data = await tb.i2c_master.read(0x70, 4)
+    await tb.i2c_master.send_stop()
+
+    tb.log.info("Read data: %s", data)
+
+    assert data == b'\x55'*4
+
+    tb.log.info("Test write to nonexistent device")
+
+    await tb.i2c_master.write(0x55, b'\x00\x04'+b'\xde\xad\xbe\xef')
+    await tb.i2c_master.send_stop()
+
+    # assert missed ack
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_i2c_single_reg(request):
+    dut = "taxi_i2c_single_reg"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "lss", f"{dut}.sv"),
+    ]
+
+    parameters = {}
+
+    parameters['FILTER_LEN'] = 4
+    parameters['DEV_ADDR'] = 0x70
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv

@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C single register testbench
+ */
+module test_taxi_i2c_single_reg #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter FILTER_LEN = 4,
+    parameter logic [6:0] DEV_ADDR = 7'h70
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+logic scl_i;
+logic scl_o;
+logic scl_t;
+logic sda_i;
+logic sda_o;
+logic sda_t;
+
+logic [7:0] data_in;
+logic data_latch;
+logic [7:0] data_out;
+
+taxi_i2c_single_reg #(
+    .FILTER_LEN(FILTER_LEN),
+    .DEV_ADDR(DEV_ADDR)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(scl_i),
+    .scl_o(scl_o),
+    .scl_t(scl_t),
+    .sda_i(sda_i),
+    .sda_o(sda_o),
+    .sda_t(sda_t),
+
+    /*
+     * Data register
+     */
+    .data_in(data_in),
+    .data_latch(data_latch),
+    .data_out(data_out)
+);
+
+endmodule
+
+`resetall