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https://github.com/fpganinja/taxi.git
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lfsr: Add LFSR CRC computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
179
rtl/lfsr/taxi_lfsr_crc.sv
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179
rtl/lfsr/taxi_lfsr_crc.sv
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* LFSR CRC generator
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*/
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module taxi_lfsr_crc #
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(
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// width of LFSR
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parameter LFSR_W = 32,
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// LFSR polynomial
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parameter logic [LFSR_W-1:0] LFSR_POLY = 32'h04c11db7,
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// Initial state
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parameter logic [LFSR_W-1:0] LFSR_INIT = '1,
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// LFSR configuration: 0 for Fibonacci (PRBS), 1 for Galois (CRC)
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parameter logic LFSR_GALOIS = 1'b1,
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// bit-reverse input and output
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parameter logic REVERSE = 1'b1,
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// invert output
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parameter logic INVERT = 1'b1,
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// width of data input and output
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parameter DATA_W = 8
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)
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(
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input wire logic clk,
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input wire logic rst,
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input wire logic [DATA_W-1:0] data_in,
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input wire logic data_in_valid,
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output wire logic [LFSR_W-1:0] crc_out
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);
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/*
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Fully parametrizable combinatorial parallel LFSR CRC module. Implements an unrolled LFSR
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next state computation.
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Ports:
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clk
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Clock input
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rst
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Reset module, set state to LFSR_INIT
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data_in
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CRC data input
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data_in_valid
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Shift input data through CRC when asserted
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data_out
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LFSR output (OUTPUT_W bits)
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Parameters:
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LFSR_W
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Specify width of LFSR/CRC register
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LFSR_POLY
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Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
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x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
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would be represented as
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32'h04c11db7
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Note that the largest term (x^32) is suppressed. This term is generated automatically based
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on LFSR_W.
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LFSR_INIT
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Initial state of LFSR. Defaults to all 1s.
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LFSR_GALOIS
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Specify the LFSR configuration, either Fibonacci (0) or Galois (1). Fibonacci is generally used
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for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
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scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
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generators and checkers.
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Fibonacci style (example for 64b66b scrambler, 0x8000000001)
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DIN (LSB first)
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V
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(+)<---------------------------(+)<-----------------------------.
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| ^ |
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| .----. .----. .----. | .----. .----. .----. |
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+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
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| '----' '----' '----' '----' '----' '----'
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V
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DOUT
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Galois style (example for CRC16, 0x8005)
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,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
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| | | ^
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| .----. .----. V .----. .----. V .----. |
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`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
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'----' '----' '----' '----' '----'
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REVERSE
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Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
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INVERT
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Bitwise invert CRC output.
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DATA_W
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Specify width of input data bus. The module will perform one shift per input data bit,
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so if the input data bus is not required tie data_in to zero and set DATA_W to the
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required number of shifts per clock cycle.
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Settings for common LFSR/CRC implementations:
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Name Configuration Length Polynomial Initial value Notes
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CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
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CRC16-CCITT Galois 16 16'h1021 16'h1d0f
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CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
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CRC32C Galois, bit-reverse 32 32'h1edc6f41 32'hffffffff iSCSI, Intel CRC32 instruction; invert final output
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*/
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logic [LFSR_W-1:0] state_reg = LFSR_INIT;
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wire [LFSR_W-1:0] lfsr_state;
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assign crc_out = INVERT ? ~state_reg : state_reg;
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taxi_lfsr #(
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.LFSR_W(LFSR_W),
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.LFSR_POLY(LFSR_POLY),
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.LFSR_GALOIS(LFSR_GALOIS),
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.LFSR_FEED_FORWARD('0),
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.REVERSE(REVERSE),
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.DATA_W(DATA_W)
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)
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lfsr_inst (
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.data_in(data_in),
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.state_in(state_reg),
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.data_out(),
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.state_out(lfsr_state)
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);
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always_ff @(posedge clk) begin
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if (data_in_valid) begin
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state_reg <= lfsr_state;
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end
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if (rst) begin
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state_reg <= LFSR_INIT;
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end
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end
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endmodule
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`resetall
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52
tb/lfsr/taxi_lfsr_crc/Makefile
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52
tb/lfsr/taxi_lfsr_crc/Makefile
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@@ -0,0 +1,52 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2023-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_lfsr_crc
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += ../../../rtl/lfsr/$(DUT).sv
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VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_LFSR_W ?= 32
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export PARAM_LFSR_POLY ?= "32'h4c11db7"
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export PARAM_LFSR_INIT ?= "'1"
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export PARAM_LFSR_GALOIS ?= "1'b1"
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export PARAM_REVERSE ?= "1'b1"
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export PARAM_INVERT ?= "1'b1"
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export PARAM_DATA_W ?= 8
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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189
tb/lfsr/taxi_lfsr_crc/test_taxi_lfsr_crc.py
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189
tb/lfsr/taxi_lfsr_crc/test_taxi_lfsr_crc.py
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@@ -0,0 +1,189 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2023-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import zlib
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import pytest
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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dut.data_in.setimmediatevalue(0)
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dut.data_in_valid.setimmediatevalue(0)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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def chunks(lst, n, padvalue=None):
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return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
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def crc32(data):
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return zlib.crc32(data) & 0xffffffff
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def crc32c(data, crc=0xffffffff, poly=0x82f63b78):
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for d in data:
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crc = crc ^ d
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for bit in range(0, 8):
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if crc & 1:
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crc = (crc >> 1) ^ poly
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else:
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crc = crc >> 1
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return ~crc & 0xffffffff
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async def run_test_crc(dut, ref_crc):
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data_width = len(dut.data_in)
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byte_lanes = data_width // 8
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tb = TB(dut)
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await tb.reset()
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block = bytes([(x+1)*0x11 for x in range(byte_lanes)])
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dut.data_in.value = int.from_bytes(block, 'little')
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dut.data_in_valid.value = 1
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await RisingEdge(dut.clk)
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dut.data_in_valid.value = 0
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await RisingEdge(dut.clk)
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val = dut.crc_out.value.integer
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ref = ref_crc(block)
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tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
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assert val == ref
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await tb.reset()
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block = bytearray(itertools.islice(itertools.cycle(range(256)), 1024))
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for b in chunks(block, byte_lanes):
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dut.data_in.value = int.from_bytes(b, 'little')
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dut.data_in_valid.value = 1
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await RisingEdge(dut.clk)
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dut.data_in_valid.value = 0
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await RisingEdge(dut.clk)
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val = dut.crc_out.value.integer
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ref = ref_crc(block)
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tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
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assert val == ref
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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if cocotb.SIM_NAME:
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if int(cocotb.top.LFSR_POLY.value) == 0x4c11db7:
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factory = TestFactory(run_test_crc)
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factory.add_option("ref_crc", [crc32])
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factory.generate_tests()
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if int(cocotb.top.LFSR_POLY.value) == 0x1edc6f41:
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factory = TestFactory(run_test_crc)
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factory.add_option("ref_crc", [crc32c])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_init", "lfsr_galois", "reverse", "invert", "data_w"), [
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(32, "32'h4c11db7", "'1", 1, 1, 1, 8),
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(32, "32'h4c11db7", "'1", 1, 1, 1, 64),
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(32, "32'h1edc6f41", "'1", 1, 1, 1, 8),
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(32, "32'h1edc6f41", "'1", 1, 1, 1, 64),
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])
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def test_taxi_lfsr_crc(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, reverse, invert, data_w):
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dut = "taxi_lfsr_crc"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, "lfsr", f"{dut}.sv"),
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os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['LFSR_W'] = lfsr_w
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parameters['LFSR_POLY'] = lfsr_poly
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parameters['LFSR_INIT'] = lfsr_init
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parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
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parameters['REVERSE'] = f"1'b{reverse}"
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parameters['INVERT'] = f"1'b{invert}"
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parameters['DATA_W'] = data_w
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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