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16 Commits 1 Branch 0 Tags
06ee1beb0ee7fd10aa9ce422264d2081ae218e20
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5 Commits

Author SHA1 Message Date
Alex Forencich
9590811570 axis: Add AXI stream pipeline FIFO module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-03 16:35:52 -08:00
Alex Forencich
47e4658b55 axis: Add AXI stream pipeline register module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-03 16:35:25 -08:00
Alex Forencich
c4558a02f0 lss: Add UART module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-03 15:02:48 -08:00
Alex Forencich
c7f719b435 axis: Add AXI stream register module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-03 12:49:08 -08:00
Alex Forencich
e1233eaffe axis: Add SV interface for AXI stream 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-02 22:45:12 -08:00