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  • 729bf79427 eth: Move link speed detection logic from MAC wrapper to PHY interface master Alex Forencich 2025-11-13 21:27:03 -08:00
  • a919552914 eth: Fix widths Alex Forencich 2025-11-13 18:07:13 -08:00
  • 4fc8baea96 eth: Update example designs for APB interface Alex Forencich 2025-11-13 18:06:33 -08:00
  • 5e77efbfe3 eth: Add APB register interface to US/US+ transceiver wrappers Alex Forencich 2025-11-13 14:15:20 -08:00
  • 2391e4f366 xfcp: Add taxi_xfcp_mod_apb.f Alex Forencich 2025-11-13 12:08:40 -08:00
  • 18f67e3faa xfcp: Fix ID string Alex Forencich 2025-11-13 12:05:19 -08:00
  • e0f570ebed eth: Add I2C to KCU105 example design Alex Forencich 2025-11-13 12:04:32 -08:00
  • 2582f86a11 eth: Move reset synchronizer to top-level of GT wrapper Alex Forencich 2025-11-13 00:02:55 -08:00
  • 898623a358 Update gitignore Alex Forencich 2025-11-12 23:39:59 -08:00
  • af9696eb06 apb: Add APB width converter module and testbench Alex Forencich 2025-11-12 23:05:12 -08:00
  • cee2ed2b31 axi: Fix names Alex Forencich 2025-11-12 22:55:39 -08:00
  • 8e3de66295 apb: Fix parameter name Alex Forencich 2025-11-12 22:07:04 -08:00
  • bfafd5777e apb: Clean up address width handling in interconnect module Alex Forencich 2025-11-12 22:02:42 -08:00
  • 8c3709d917 axi: Clean up address width handling in interconnect modules Alex Forencich 2025-11-12 22:01:45 -08:00
  • dd4c639600 axi: Remove extraneous code Alex Forencich 2025-11-12 21:43:42 -08:00
  • f472fda1e4 apb: Fix interface indexing Alex Forencich 2025-11-12 21:42:39 -08:00
  • 92baa34b54 axi: Fix interface indexing Alex Forencich 2025-11-12 21:42:12 -08:00
  • b4d958d477 axis: Use bin2gray function in async FIFO Alex Forencich 2025-11-12 17:05:38 -08:00
  • ee31bbf936 axi: Minor cleanup in AXIL-APB adapter module Alex Forencich 2025-11-12 17:04:59 -08:00
  • 18794f33c9 apb: Add APB interconnect module and testbench Alex Forencich 2025-11-12 17:04:07 -08:00
  • 32200d9009 Update readme Alex Forencich 2025-11-11 23:23:47 -08:00
  • baa9822580 ci: Update to verilator 5.038 Alex Forencich 2025-11-11 22:55:32 -08:00
  • ccb024f8ce axi: Add AXI crossbar module and testbench Alex Forencich 2025-11-11 22:33:31 -08:00
  • 0a4da49c74 axi: Makefile parameter cleanup Alex Forencich 2025-11-11 20:31:24 -08:00
  • cbbad58efb axi: Fix sideband signal handling in AXI lite crossbar Alex Forencich 2025-11-11 17:31:44 -08:00
  • 053c9368e9 axi: Add AXI lite crossbar module and testbench Alex Forencich 2025-11-11 15:06:32 -08:00
  • d68d421694 axi: Dereference interface arrays in interconnect modules when extracting parameters Alex Forencich 2025-11-11 14:32:50 -08:00
  • 3d5a9efdb8 axi: Add AXI interconnect module and testbench Alex Forencich 2025-11-11 12:40:07 -08:00
  • 34dd338acf axi: Add AXI lite interconnect module and testbench Alex Forencich 2025-11-11 10:20:26 -08:00
  • 3519abbee5 eth: Add support for 10GBASE-R to KC705 example design Alex Forencich 2025-11-09 14:24:05 -08:00
  • 4e256cfe37 eth: Add support for 7-series GTX transceiver to 10G/25G MAC Alex Forencich 2025-11-09 13:39:14 -08:00
  • 44ebbbbc87 eth: KC705 cleanup, add I2C Alex Forencich 2025-11-09 13:37:10 -08:00
  • 6054f76a17 eth: Add Ethernet example design for NetFPGA SUME Alex Forencich 2025-11-08 19:46:20 -08:00
  • 4dbfc4d388 eth: Add Ethernet example design for VC709 Alex Forencich 2025-11-08 16:06:12 -08:00
  • 2d061a76f2 eth: Add support for 7-series GTH transceiver to 10G/25G MAC Alex Forencich 2025-11-08 00:39:50 -08:00
  • 32eed71e89 eth: Clean up MAC wrappers Alex Forencich 2025-11-07 12:26:12 -08:00
  • 1cd6275877 eth: Update ZCU111 example XDC Alex Forencich 2025-11-07 12:24:00 -08:00
  • 1e8917affb eth: Update KCU105 example XDC Alex Forencich 2025-11-07 12:23:12 -08:00
  • cae7053e78 eth: Update KC705 example XDC Alex Forencich 2025-11-07 12:23:00 -08:00
  • 004246608e Use logic instead of reg Alex Forencich 2025-11-07 02:14:19 -08:00
  • 5f814e7da8 Clean up always blocks Alex Forencich 2025-11-07 01:51:18 -08:00
  • efc907e4c9 axis: Add assertions to FIFO modules for USER_EN settings Alex Forencich 2025-11-06 17:58:33 -08:00
  • 9009880073 eth: Enable tuser signal in example designs Alex Forencich 2025-11-06 17:44:50 -08:00
  • 434f31887e eth: Use tie and null_src modules Alex Forencich 2025-11-06 09:35:26 -08:00
  • c6eac348f6 eth: Update HTG-9200 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-06 00:49:50 -08:00
  • 0fe56c5390 eth: Update Alveo example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 23:42:03 -08:00
  • b97eb139ca eth: Update XUPP3R/XUSP3S example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 22:02:32 -08:00
  • 66a93a734f eth: Update HTG-ZRF8-EM/R2 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 21:54:04 -08:00
  • 06eb4aafcd eth: Update VCU118 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 21:51:40 -08:00
  • 0f5bc4eba8 eth: Update VCU108 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 21:49:33 -08:00
  • 31081b6a23 eth: Update fb2CG@KU15P example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 21:49:09 -08:00
  • c2858c183e eth: Fix typo in fb2CG@KU15P example design Alex Forencich 2025-11-05 21:28:42 -08:00
  • a7b2db9c20 eth: Update Nexus K35-S/K3P-S example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 20:50:32 -08:00
  • ae05128b44 eth: Update Nexus K3P-Q example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 20:46:30 -08:00
  • 4682591ec3 eth: Update ZCU111 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 18:08:19 -08:00
  • 3c40ce964b eth: Update AS02MC04 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 17:59:46 -08:00
  • 40cc51d062 eth: Update ZCU106 example design testbench to test both 32-bit and 64-bit configurations Alex Forencich 2025-11-05 15:37:49 -08:00
  • 7dbe595e5b eth: Update ADM-PCIE-9V3 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 15:36:49 -08:00
  • 77313e1ed0 eth: Add example design for Alibaba AS02MC04 Alex Forencich 2025-11-05 14:35:33 -08:00
  • 3b95e2f279 dma: Remove unnecessary handshake condition Alex Forencich 2025-11-04 17:45:54 -08:00
  • b0dd91aa8d dma: Add UltraScale PCIe DMA interface module and testbench Alex Forencich 2025-11-04 17:18:26 -08:00
  • 14d988d1f2 dma: Add AXI DMA interface module and testbench Alex Forencich 2025-11-04 12:41:07 -08:00
  • 851919f16f dma: Add AXI stream sink DMA client module and testbench Alex Forencich 2025-11-03 21:30:55 -08:00
  • 5663572421 dma: Add AXI stream source DMA client module and testbench Alex Forencich 2025-11-03 21:30:20 -08:00
  • 5b0c83fc57 dma: Add AXI streaming DMA module and testbench Alex Forencich 2025-11-03 17:14:24 -08:00
  • 9442bb7fbb dma: Add AXI central DMA module and testbench Alex Forencich 2025-11-03 11:42:04 -08:00
  • 999602cf11 Update readme Alex Forencich 2025-11-03 09:24:04 -08:00
  • 4b7e3d066d dma: Add SV interface for DMA descriptors Alex Forencich 2025-11-03 09:23:46 -08:00
  • 4e099af53a math: Add MT19937 Mersenne Twister PRNG module and testbench Alex Forencich 2025-10-15 22:14:21 -07:00
  • 7ec62b6b47 eth: Push CRC computation logic towards input in 64-bit BASE-R RX module Alex Forencich 2025-10-05 19:34:27 -07:00
  • f6bfd0d097 eth: Push CRC computation logic towards input in 64-bit XGMII RX module Alex Forencich 2025-10-05 19:10:30 -07:00
  • ae53b5d286 eth: Push CRC computation logic towards input in 32-bit XGMII RX module Alex Forencich 2025-10-05 19:09:59 -07:00
  • adf10be684 eth: Remove unused rxc regs Alex Forencich 2025-10-05 18:12:50 -07:00
  • 08879e80b8 eth: Mask off end of packet when lane swapped Alex Forencich 2025-10-05 18:12:20 -07:00
  • 59a3d5f511 eth: Normalize signal and register names in MAC modules Alex Forencich 2025-10-05 18:11:27 -07:00
  • 2810b72147 eth: Decoding is don't care with termination in lane 0 Alex Forencich 2025-10-04 21:59:20 -07:00
  • caeacadb78 eth: Clean up masking, lane 0 never needs to be masked Alex Forencich 2025-10-04 20:06:58 -07:00
  • 93ef0f970b eth: Re-nest if statements for termination character handling in 10G RX logic Alex Forencich 2025-10-04 19:01:47 -07:00
  • e395398666 eth: Rework input encoding in BASE-R RX modules Alex Forencich 2025-10-04 18:43:20 -07:00
  • 7e08164e8d eth: Add term_first_cycle_reg to reduce fanin Alex Forencich 2025-10-04 17:01:53 -07:00
  • 879b65cc70 eth: Normalize CRC register naming in 10G RX modules Alex Forencich 2025-10-04 15:54:49 -07:00
  • d0d6747f88 eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module Alex Forencich 2025-10-04 11:47:21 -07:00
  • 0e2acbf482 eth: Fix 2D array declarations Alex Forencich 2025-10-04 11:02:30 -07:00
  • 5dff55ec06 lfsr: Remove extraneous data mask init Alex Forencich 2025-10-03 22:08:57 -07:00
  • 04df834708 eth: Optimize frame length enforcement logic in BASE-R MACs Alex Forencich 2025-10-03 15:49:51 -07:00
  • 8257fdf09e eth: Remove unused encodings Alex Forencich 2025-10-03 13:47:52 -07:00
  • 144537126a axis: Remove extraneous generate block in async FIFO Alex Forencich 2025-10-02 23:36:25 -07:00
  • f4e36bd081 eth: Optimize padding logic in BASE-R MACs Alex Forencich 2025-10-02 23:08:11 -07:00
  • 7e629d934f Fix TX enable in AXI stream BASE-R TX module Alex Forencich 2025-10-02 20:44:43 -07:00
  • 159c9d6241 eth: Update example designs Alex Forencich 2025-10-02 16:11:07 -07:00
  • 76d4465081 eth: Convert UltraScale wrapper to use unpacked arrays for channels Alex Forencich 2025-10-02 16:10:37 -07:00
  • a74a49cffb xfcp: Add XFCP module for APB Alex Forencich 2025-09-30 21:01:17 -07:00
  • 86f52189b5 xfcp: Symlinks for common testbench code Alex Forencich 2025-09-30 20:59:58 -07:00
  • 8f5a534d35 axi: Tie off ruser/buser in AXI lite RAM modules Alex Forencich 2025-09-30 16:30:32 -07:00
  • bdfc0f120c axi: Tie off ruser/buser in AXI RAM module Alex Forencich 2025-09-30 16:28:59 -07:00
  • 88018ac9e8 axi: Add AXI lite to APB adapter module and testbench Alex Forencich 2025-09-30 16:14:17 -07:00
  • 952232ad66 apb: Add APB dual-port RAM module and testbench Alex Forencich 2025-09-30 15:25:21 -07:00
  • f25e41de18 apb: Add APB RAM module and testbench Alex Forencich 2025-09-30 15:24:56 -07:00
  • f4f473afeb apb: Add user sideband signals to APB interface Alex Forencich 2025-09-30 15:19:07 -07:00
  • e836357c33 ci: Update packages Alex Forencich 2025-09-30 14:38:49 -07:00