bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2026-01-18 01:30:36 -08:00
Code Issues Packages Projects Releases Wiki Activity

Commit Graph

  • 62da198a76 dma: Remove extraneous comma master Alex Forencich 2026-01-18 00:13:18 -08:00
  • 8328f50673 lss: Add I2C slave APB master module and testbench Alex Forencich 2026-01-13 18:25:06 -08:00
  • 9e8925de39 lss: Tie off unused interface signals Alex Forencich 2026-01-13 15:59:06 -08:00
  • 9e336fbdd5 Update readme Alex Forencich 2026-01-12 00:19:18 -08:00
  • bedd85d7f6 Update readme Alex Forencich 2026-01-10 00:35:42 -08:00
  • be40d3ac2d eth: Update example design readme Alex Forencich 2026-01-09 16:43:01 -08:00
  • 329fcf1f45 cndm_proto: Add some comments to core HDL Alex Forencich 2026-01-09 00:05:10 -08:00
  • 4b3a4b4059 eth: Capture TX tag on the first cylce of the packet Alex Forencich 2026-01-03 23:44:53 -08:00
  • 108fb10735 cndm_proto: Remove padding bug workaround Alex Forencich 2026-01-02 01:24:51 -08:00
  • 3c4aecc859 cndm: Remove padding bug workaround Alex Forencich 2026-01-02 01:24:42 -08:00
  • 711b268cb7 cndm_proto: Clean up tests Alex Forencich 2026-01-02 01:24:21 -08:00
  • 2987c8db71 cndm: Clean up tests Alex Forencich 2026-01-02 01:24:08 -08:00
  • d1bba66104 eth: Fix MAC padding bug in 32-bit MACs Alex Forencich 2026-01-02 01:19:53 -08:00
  • 77b50c7f85 cndm_proto: Support changing MAC address Alex Forencich 2026-01-01 22:13:03 -08:00
  • 541f6a9ee6 cndm: Support changing MAC address Alex Forencich 2026-01-01 22:12:38 -08:00
  • eca44dc247 cndm: Allocate IRQ structures in one block Alex Forencich 2026-01-01 22:04:13 -08:00
  • 107238cce2 cndm_proto: Use ARRAY_SIZE Alex Forencich 2026-01-01 21:51:26 -08:00
  • 38d13f8337 cndm: Use ARRAY_SIZE Alex Forencich 2026-01-01 21:51:14 -08:00
  • 847d47b71f cndm_proto: Replace DRIVER_NAME with KBUILD_MODNAME Alex Forencich 2026-01-01 21:45:11 -08:00
  • b8cd443e01 cndm: Replace DRIVER_NAME with KBUILD_MODNAME Alex Forencich 2026-01-01 21:41:45 -08:00
  • d554f45b22 cndm: Register regions with the instance name instead of the module name Alex Forencich 2026-01-01 21:35:59 -08:00
  • c18aed2074 cndm: Print PCIe configuration summary Alex Forencich 2026-01-01 21:19:19 -08:00
  • 3e421e3cdd cndm: Implement mmap and ioctl Alex Forencich 2026-01-01 15:07:50 -08:00
  • a0e6ac2c35 cndm: Ensure IDA is cleaned up on module unload Alex Forencich 2026-01-01 01:42:52 -08:00
  • 0c0ac88462 cndm: Factor out common probe/remove code Alex Forencich 2026-01-01 01:33:58 -08:00
  • fb93b62c50 cndm: Use notifier chain for interrupts Alex Forencich 2026-01-01 01:31:39 -08:00
  • ecf62c94e6 cndm: Add support for ethtool Alex Forencich 2025-12-31 23:58:10 -08:00
  • cc4e465462 cndm: Register misc device Alex Forencich 2025-12-31 23:48:50 -08:00
  • 96e24756de cndm: Assign instance ID Alex Forencich 2025-12-31 23:36:19 -08:00
  • 8ad1842b90 cndm: Add support for devlink Alex Forencich 2025-12-31 23:18:56 -08:00
  • fc395b1596 cndm: Update C file headers Alex Forencich 2025-12-31 22:29:42 -08:00
  • 8f60b25205 cndm_proto: Update C file headers Alex Forencich 2025-12-31 22:29:23 -08:00
  • 2c45420b52 cndm: Add corundum-micro design for AS02MC04 Alex Forencich 2025-12-31 18:53:50 -08:00
  • d2f56bb932 cndm: Initial commit of corundum-micro Alex Forencich 2025-12-31 18:53:30 -08:00
  • 3fcb32f232 cndm_proto: Add corundum-proto design for AS02MC04 Alex Forencich 2025-12-31 17:40:42 -08:00
  • 74e49a77e2 cndm_proto: Initial commit of corundum-proto Alex Forencich 2025-12-31 17:32:18 -08:00
  • 4da6771603 dma: Prevent width-related warnings when optional AXI stream sideband signals are not used Alex Forencich 2025-12-31 13:02:26 -08:00
  • 245e71551b pcie: Add MSI shim for UltraScale Alex Forencich 2025-12-23 18:03:56 -08:00
  • bfb96c677a dma: Add DMA interface mux modules Alex Forencich 2025-12-23 18:02:19 -08:00
  • 2ada85105f dma: Add DMA RAM demux modules Alex Forencich 2025-12-23 18:01:57 -08:00
  • 9d8c5fce73 dma: Add DMA descriptor mux module Alex Forencich 2025-12-23 18:01:40 -08:00
  • 8bff361e12 axi: Add AXI crossbar 1S wrappers and testbench Alex Forencich 2025-12-23 17:50:08 -08:00
  • 2455b770fd axi: Add AXI interconnect 1S wrappers and testbench Alex Forencich 2025-12-23 17:49:55 -08:00
  • 900483d0cd axi: Add AXI-lite crossbar 1S wrappers and testbench Alex Forencich 2025-12-23 17:46:13 -08:00
  • ec7610754c axi: Add AXI-lite interconnect 1S wrappers and testbench Alex Forencich 2025-12-23 17:45:50 -08:00
  • bef82674d3 axi: Add AXI tie modules Alex Forencich 2025-12-23 17:37:43 -08:00
  • 83c52e6744 axi: Add AXI-lite tie modules Alex Forencich 2025-12-23 17:37:36 -08:00
  • dfe13db9f7 axi: Sweep burst size in AXI interconnect tests Alex Forencich 2025-12-23 17:28:11 -08:00
  • 008e06ff48 dma: Cast RAM address width appropriately Alex Forencich 2025-12-15 20:53:15 -08:00
  • ec00c2323c dma: Cast PCIe TLP tag width appropriately Alex Forencich 2025-12-15 20:22:29 -08:00
  • cb3538a0de dma: Add interface configuration checks to DMA PSDPRAM module Alex Forencich 2025-12-15 20:21:24 -08:00
  • cbe0fa730d dma: Add missing ASID signals to DMA descriptor interface Alex Forencich 2025-12-15 20:12:42 -08:00
  • 7449dcfdc3 eth/example: Use logging.getLogger instead of SimLog Alex Forencich 2025-11-17 21:34:06 -08:00
  • 75d28d5adb eth: Clean up MGT pin connections in example designs Alex Forencich 2025-11-14 12:07:26 -08:00
  • 729bf79427 eth: Move link speed detection logic from MAC wrapper to PHY interface Alex Forencich 2025-11-13 21:27:03 -08:00
  • a919552914 eth: Fix widths Alex Forencich 2025-11-13 18:07:13 -08:00
  • 4fc8baea96 eth: Update example designs for APB interface Alex Forencich 2025-11-13 18:06:33 -08:00
  • 5e77efbfe3 eth: Add APB register interface to US/US+ transceiver wrappers Alex Forencich 2025-11-13 14:15:20 -08:00
  • 2391e4f366 xfcp: Add taxi_xfcp_mod_apb.f Alex Forencich 2025-11-13 12:08:40 -08:00
  • 18f67e3faa xfcp: Fix ID string Alex Forencich 2025-11-13 12:05:19 -08:00
  • e0f570ebed eth: Add I2C to KCU105 example design Alex Forencich 2025-11-13 12:04:32 -08:00
  • 2582f86a11 eth: Move reset synchronizer to top-level of GT wrapper Alex Forencich 2025-11-13 00:02:55 -08:00
  • 898623a358 Update gitignore Alex Forencich 2025-11-12 23:39:59 -08:00
  • af9696eb06 apb: Add APB width converter module and testbench Alex Forencich 2025-11-12 23:05:12 -08:00
  • cee2ed2b31 axi: Fix names Alex Forencich 2025-11-12 22:55:39 -08:00
  • 8e3de66295 apb: Fix parameter name Alex Forencich 2025-11-12 22:07:04 -08:00
  • bfafd5777e apb: Clean up address width handling in interconnect module Alex Forencich 2025-11-12 22:02:42 -08:00
  • 8c3709d917 axi: Clean up address width handling in interconnect modules Alex Forencich 2025-11-12 22:01:45 -08:00
  • dd4c639600 axi: Remove extraneous code Alex Forencich 2025-11-12 21:43:42 -08:00
  • f472fda1e4 apb: Fix interface indexing Alex Forencich 2025-11-12 21:42:39 -08:00
  • 92baa34b54 axi: Fix interface indexing Alex Forencich 2025-11-12 21:42:12 -08:00
  • b4d958d477 axis: Use bin2gray function in async FIFO Alex Forencich 2025-11-12 17:05:38 -08:00
  • ee31bbf936 axi: Minor cleanup in AXIL-APB adapter module Alex Forencich 2025-11-12 17:04:59 -08:00
  • 18794f33c9 apb: Add APB interconnect module and testbench Alex Forencich 2025-11-12 17:04:07 -08:00
  • 32200d9009 Update readme Alex Forencich 2025-11-11 23:23:47 -08:00
  • baa9822580 ci: Update to verilator 5.038 Alex Forencich 2025-11-11 22:55:32 -08:00
  • ccb024f8ce axi: Add AXI crossbar module and testbench Alex Forencich 2025-11-11 22:33:31 -08:00
  • 0a4da49c74 axi: Makefile parameter cleanup Alex Forencich 2025-11-11 20:31:24 -08:00
  • cbbad58efb axi: Fix sideband signal handling in AXI lite crossbar Alex Forencich 2025-11-11 17:31:44 -08:00
  • 053c9368e9 axi: Add AXI lite crossbar module and testbench Alex Forencich 2025-11-11 15:06:32 -08:00
  • d68d421694 axi: Dereference interface arrays in interconnect modules when extracting parameters Alex Forencich 2025-11-11 14:32:50 -08:00
  • 3d5a9efdb8 axi: Add AXI interconnect module and testbench Alex Forencich 2025-11-11 12:40:07 -08:00
  • 34dd338acf axi: Add AXI lite interconnect module and testbench Alex Forencich 2025-11-11 10:20:26 -08:00
  • 3519abbee5 eth: Add support for 10GBASE-R to KC705 example design Alex Forencich 2025-11-09 14:24:05 -08:00
  • 4e256cfe37 eth: Add support for 7-series GTX transceiver to 10G/25G MAC Alex Forencich 2025-11-09 13:39:14 -08:00
  • 44ebbbbc87 eth: KC705 cleanup, add I2C Alex Forencich 2025-11-09 13:37:10 -08:00
  • 6054f76a17 eth: Add Ethernet example design for NetFPGA SUME Alex Forencich 2025-11-08 19:46:20 -08:00
  • 4dbfc4d388 eth: Add Ethernet example design for VC709 Alex Forencich 2025-11-08 16:06:12 -08:00
  • 2d061a76f2 eth: Add support for 7-series GTH transceiver to 10G/25G MAC Alex Forencich 2025-11-08 00:39:50 -08:00
  • 32eed71e89 eth: Clean up MAC wrappers Alex Forencich 2025-11-07 12:26:12 -08:00
  • 1cd6275877 eth: Update ZCU111 example XDC Alex Forencich 2025-11-07 12:24:00 -08:00
  • 1e8917affb eth: Update KCU105 example XDC Alex Forencich 2025-11-07 12:23:12 -08:00
  • cae7053e78 eth: Update KC705 example XDC Alex Forencich 2025-11-07 12:23:00 -08:00
  • 004246608e Use logic instead of reg Alex Forencich 2025-11-07 02:14:19 -08:00
  • 5f814e7da8 Clean up always blocks Alex Forencich 2025-11-07 01:51:18 -08:00
  • efc907e4c9 axis: Add assertions to FIFO modules for USER_EN settings Alex Forencich 2025-11-06 17:58:33 -08:00
  • 9009880073 eth: Enable tuser signal in example designs Alex Forencich 2025-11-06 17:44:50 -08:00
  • 434f31887e eth: Use tie and null_src modules Alex Forencich 2025-11-06 09:35:26 -08:00
  • c6eac348f6 eth: Update HTG-9200 example design to use 32-bit MACs at 10G Alex Forencich 2025-11-06 00:49:50 -08:00
  • 0fe56c5390 eth: Update Alveo example design to use 32-bit MACs at 10G Alex Forencich 2025-11-05 23:42:03 -08:00