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• 851919f16f dma: Add AXI stream sink DMA client module and testbench Alex Forencich 2025-11-03 21:30:55 -08:00
• 5663572421 dma: Add AXI stream source DMA client module and testbench Alex Forencich 2025-11-03 21:30:20 -08:00
• 5b0c83fc57 dma: Add AXI streaming DMA module and testbench Alex Forencich 2025-11-03 17:14:24 -08:00
• 9442bb7fbb dma: Add AXI central DMA module and testbench Alex Forencich 2025-11-03 11:42:04 -08:00
• 999602cf11 Update readme Alex Forencich 2025-11-03 09:24:04 -08:00
• 4b7e3d066d dma: Add SV interface for DMA descriptors Alex Forencich 2025-11-03 09:23:46 -08:00
• 4e099af53a math: Add MT19937 Mersenne Twister PRNG module and testbench Alex Forencich 2025-10-15 22:14:21 -07:00
• 7ec62b6b47 eth: Push CRC computation logic towards input in 64-bit BASE-R RX module Alex Forencich 2025-10-05 19:34:27 -07:00
• f6bfd0d097 eth: Push CRC computation logic towards input in 64-bit XGMII RX module Alex Forencich 2025-10-05 19:10:30 -07:00
• ae53b5d286 eth: Push CRC computation logic towards input in 32-bit XGMII RX module Alex Forencich 2025-10-05 19:09:59 -07:00
• adf10be684 eth: Remove unused rxc regs Alex Forencich 2025-10-05 18:12:50 -07:00
• 08879e80b8 eth: Mask off end of packet when lane swapped Alex Forencich 2025-10-05 18:12:20 -07:00
• 59a3d5f511 eth: Normalize signal and register names in MAC modules Alex Forencich 2025-10-05 18:11:27 -07:00
• 2810b72147 eth: Decoding is don't care with termination in lane 0 Alex Forencich 2025-10-04 21:59:20 -07:00
• caeacadb78 eth: Clean up masking, lane 0 never needs to be masked Alex Forencich 2025-10-04 20:06:58 -07:00
• 93ef0f970b eth: Re-nest if statements for termination character handling in 10G RX logic Alex Forencich 2025-10-04 19:01:47 -07:00
• e395398666 eth: Rework input encoding in BASE-R RX modules Alex Forencich 2025-10-04 18:43:20 -07:00
• 7e08164e8d eth: Add term_first_cycle_reg to reduce fanin Alex Forencich 2025-10-04 17:01:53 -07:00
• 879b65cc70 eth: Normalize CRC register naming in 10G RX modules Alex Forencich 2025-10-04 15:54:49 -07:00
• d0d6747f88 eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module Alex Forencich 2025-10-04 11:47:21 -07:00
• 0e2acbf482 eth: Fix 2D array declarations Alex Forencich 2025-10-04 11:02:30 -07:00
• 5dff55ec06 lfsr: Remove extraneous data mask init Alex Forencich 2025-10-03 22:08:57 -07:00
• 04df834708 eth: Optimize frame length enforcement logic in BASE-R MACs Alex Forencich 2025-10-03 15:49:51 -07:00
• 8257fdf09e eth: Remove unused encodings Alex Forencich 2025-10-03 13:47:52 -07:00
• 144537126a axis: Remove extraneous generate block in async FIFO Alex Forencich 2025-10-02 23:36:25 -07:00
• f4e36bd081 eth: Optimize padding logic in BASE-R MACs Alex Forencich 2025-10-02 23:08:11 -07:00
• 7e629d934f Fix TX enable in AXI stream BASE-R TX module Alex Forencich 2025-10-02 20:44:43 -07:00
• 159c9d6241 eth: Update example designs Alex Forencich 2025-10-02 16:11:07 -07:00
• 76d4465081 eth: Convert UltraScale wrapper to use unpacked arrays for channels Alex Forencich 2025-10-02 16:10:37 -07:00
• a74a49cffb xfcp: Add XFCP module for APB Alex Forencich 2025-09-30 21:01:17 -07:00
• 86f52189b5 xfcp: Symlinks for common testbench code Alex Forencich 2025-09-30 20:59:58 -07:00
• 8f5a534d35 axi: Tie off ruser/buser in AXI lite RAM modules Alex Forencich 2025-09-30 16:30:32 -07:00
• bdfc0f120c axi: Tie off ruser/buser in AXI RAM module Alex Forencich 2025-09-30 16:28:59 -07:00
• 88018ac9e8 axi: Add AXI lite to APB adapter module and testbench Alex Forencich 2025-09-30 16:14:17 -07:00
• 952232ad66 apb: Add APB dual-port RAM module and testbench Alex Forencich 2025-09-30 15:25:21 -07:00
• f25e41de18 apb: Add APB RAM module and testbench Alex Forencich 2025-09-30 15:24:56 -07:00
• f4f473afeb apb: Add user sideband signals to APB interface Alex Forencich 2025-09-30 15:19:07 -07:00
• e836357c33 ci: Update packages Alex Forencich 2025-09-30 14:38:49 -07:00
• 38ae0c1587 eth: Clean up casts Alex Forencich 2025-09-07 15:18:23 -07:00
• 9307e0df6c pcie: Clean up casts Alex Forencich 2025-09-07 15:17:46 -07:00
• 1e12094f45 stats: Clean up casts Alex Forencich 2025-09-07 14:58:16 -07:00
• 32ed95893c dma: Clean up casts in DMA PSDPRAM model Alex Forencich 2025-09-07 14:37:41 -07:00
• e42a2dd8b4 lss: Use cocotb.start_soon instead of cocotb.fork Alex Forencich 2025-09-07 14:36:27 -07:00
• 6a5faf9ebf Cast to int instead of using .integer Alex Forencich 2025-09-07 11:25:34 -07:00
• 40908b1b92 Testbench cleanup for cocotb 2.0 Alex Forencich 2025-09-07 10:59:38 -07:00
• 884fe1a006 apb: Add lib symlink Alex Forencich 2025-09-06 16:50:44 -07:00
• 81a918d223 apb: Add SV interface for APB Alex Forencich 2025-09-06 16:50:38 -07:00
• 20f14ace97 Update readme Alex Forencich 2025-09-06 07:06:50 -07:00
• 553dea534e eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2 Alex Forencich 2025-09-06 07:03:35 -07:00
• 0d7e0cf590 eth/example/ZCU111: Clean up RFDC clocking Alex Forencich 2025-09-05 07:30:30 -07:00
• 6c9026bccf eth/example/HTG9200: Fix refclock frequency in testbench Alex Forencich 2025-09-05 07:15:26 -07:00
• 2ae5b5fae3 pcie: Remove TLP_HDR_W parameter from testbenches Alex Forencich 2025-09-01 22:08:18 -07:00
• cdfb1566f5 Update readme Alex Forencich 2025-08-31 21:38:06 -07:00
• a6db298eeb dma: Add async DMA PSDPRAM module and testbench Alex Forencich 2025-08-31 21:30:25 -07:00
• 48da5315fe dma: Add DMA PSDPRAM module and testbench Alex Forencich 2025-08-31 21:29:55 -07:00
• d57b49b29c dma: Add PSDPRAM simulation model Alex Forencich 2025-08-31 21:05:20 -07:00
• c5fea4d920 dma: Add lib symlink Alex Forencich 2025-08-31 21:04:44 -07:00
• 10500e6c6c dma: Add DMA RAM interface Alex Forencich 2025-08-31 21:04:22 -07:00
• e87e16c299 axi: Add AXI FIFO module and testbench Alex Forencich 2025-08-30 22:17:53 -07:00
• 0080125120 axi: Add AXI to AXI lite adapter module and testbench Alex Forencich 2025-08-30 21:11:20 -07:00
• 94a821192c axi: Add AXI width converter module and testbench Alex Forencich 2025-08-30 21:10:08 -07:00
• 5f6487964e axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface Alex Forencich 2025-08-30 13:55:33 -07:00
• e43d6acbbd axi: Add AXI lite to AXI adapter module and testbench Alex Forencich 2025-08-30 13:40:43 -07:00
• c22e659259 axi: Add AXI lite width converter module and testbench Alex Forencich 2025-08-30 13:02:27 -07:00
• 4dd84efd6c Update readme Alex Forencich 2025-08-29 18:00:22 -07:00
• bf584147a1 pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master Alex Forencich 2025-08-29 17:59:56 -07:00
• b3441f6408 pcie: Rename enable to en in PCIe US AXI lite master Alex Forencich 2025-08-29 17:59:33 -07:00
• 63c961cab4 pcie: Fix some corner cases in PCIe US AXI lite master Alex Forencich 2025-08-29 16:50:31 -07:00
• b5c9c02b03 pcie: Add UltraScale PCIe AXI Lite Master module and testbench Alex Forencich 2025-08-25 22:39:28 -07:00
• 06e6f3e1b4 lss: Optimize delay implementation in I2C master module Alex Forencich 2025-08-24 11:30:03 -07:00
• c2c4f5316d xfcp: Fix width Alex Forencich 2025-08-24 11:26:25 -07:00
• 07ae2ba989 eth: Add RFDC to ZCU111 example design Alex Forencich 2025-08-24 11:26:14 -07:00
• 4c43b68f94 eth: Add 6QSFP FMC support to HTG9200 example design Alex Forencich 2025-08-20 16:24:39 -07:00
• cf0ec74849 eth: HTG9200 example design cleanup Alex Forencich 2025-08-20 06:37:14 -07:00
• 5e890bc6cd axis: Add AXI stream tie and null source/sink modules Alex Forencich 2025-08-20 06:33:21 -07:00
• a8dbe26f12 zircon: tdest not used on TX path after length/checksum computation, which also extracts the tdest value Alex Forencich 2025-08-15 13:36:14 -07:00
• 3a07e3e28c zircon: Improve sideband signal handling in length/checksum computation module Alex Forencich 2025-08-15 13:34:15 -07:00
• d0efd5f24c zircon: Connect tdest Alex Forencich 2025-08-14 14:11:55 -07:00
• 9955b79fcd zircon: Add FIFO configuration parameters Alex Forencich 2025-08-13 17:17:34 -07:00
• af8daa89ce zircon: Fix flow control bug in parser Alex Forencich 2025-08-13 13:44:49 -07:00
• 0aad8ef2cc zircon: Fix testbench Alex Forencich 2025-08-06 15:33:05 -07:00
• e5ce27cc30 zircon: Add lib symlink Alex Forencich 2025-08-06 15:13:47 -07:00
• 67bfb947f4 zircon: Add TX buffer module Alex Forencich 2025-08-06 15:09:04 -07:00
• 18fdf53d5d zircon: Add ingress and egress modules Alex Forencich 2025-08-06 15:08:40 -07:00
• 48465423fb zircon: Add length and checksum computation module and testbench Alex Forencich 2025-08-06 15:06:12 -07:00
• 7c1f2652b6 zircon: Add TX deparser module and testbench Alex Forencich 2025-08-06 14:57:14 -07:00
• babce69bd0 zircon: Add RX parser module and testbench Alex Forencich 2025-08-06 14:49:22 -07:00
• 65cb6124c4 Update readme Alex Forencich 2025-08-02 21:20:34 -07:00
• a16a667f81 lss: Add I2C init module Alex Forencich 2025-08-02 21:20:21 -07:00
• d4089096ae example: Add example design for HTG-9200 Alex Forencich 2025-08-02 21:19:58 -07:00
• 467b044e88 lss: Add missing file list file handling Alex Forencich 2025-08-02 15:15:29 -07:00
• 89f60f26ff lss: Add some interface configuration checks to I2C modules Alex Forencich 2025-08-02 14:40:56 -07:00
• 8017534c45 lss: Rename I2C data ports to reduce ambiguity Alex Forencich 2025-08-02 14:40:33 -07:00
• 4620370035 lss: Add I2C slave AXI lite master module and testbench Alex Forencich 2025-08-02 00:44:14 -07:00
• 37825a02f4 lss: Add I2C slave module and testbench Alex Forencich 2025-08-02 00:22:11 -07:00
• 8bcd7ca037 axis: Expand size range for concatenator module tests Alex Forencich 2025-07-31 14:13:13 -07:00
• 933899887a axis: Add AXI stream switch module and testbench Alex Forencich 2025-07-31 11:47:49 -07:00
• dd8b2a89ed axis: Remove unnecessary idle cycles in taxi_axis_concat Alex Forencich 2025-07-30 22:03:16 -07:00
• bd0b0cd75a Update documentation URL Alex Forencich 2025-07-30 19:12:45 -07:00
• d10e3cf5c0 axis: Add AXI stream demultiplexer module and testbench Alex Forencich 2025-07-30 19:10:48 -07:00