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  • 36ea9fb8d4 example/Arty: Clean up Arty example design Alex Forencich 2025-02-18 00:55:08 -08:00
  • db183c7bdd Add test durations for pytest-split Alex Forencich 2025-02-17 18:10:01 -08:00
  • 6577d016e5 Run example design testbenches in CI Alex Forencich 2025-02-17 00:26:06 -08:00
  • 2c6fac0b9d Update readme Alex Forencich 2025-02-17 00:13:51 -08:00
  • dd2a0d1bf3 example: Add example design for Arty A7 Alex Forencich 2025-02-17 00:13:06 -08:00
  • c6ca108392 eth: Clean up testbench clocking Alex Forencich 2025-02-16 22:45:19 -08:00
  • 689cd34739 eth: Add additional Ethernet MAC-related timing constraints Alex Forencich 2025-02-16 22:30:15 -08:00
  • 1112545d0a Update readme Alex Forencich 2025-02-16 22:22:43 -08:00
  • 94dba88560 eth: Add RGMII Ethernet MAC with FIFOs module and testbench Alex Forencich 2025-02-16 22:17:42 -08:00
  • 255b26d2f2 eth: Add GMII Ethernet MAC with FIFOs module and testbench Alex Forencich 2025-02-16 22:17:22 -08:00
  • baa5f72a6c eth: Add MII Ethernet MAC with FIFOs module and testbench Alex Forencich 2025-02-16 22:16:54 -08:00
  • ffaf05f2d1 eth: Add RGMII Ethernet MAC module and testbench Alex Forencich 2025-02-16 22:05:59 -08:00
  • fab49d1435 eth: Add RGMII PHY interface module Alex Forencich 2025-02-16 21:50:42 -08:00
  • c0583aaff5 eth: Add GMII Ethernet MAC module and testbench Alex Forencich 2025-02-16 21:37:12 -08:00
  • 1dc5463f00 eth: Add GMII PHY interface module Alex Forencich 2025-02-16 21:34:49 -08:00
  • 175230eeaf eth: Add MII Ethernet MAC module and testbench Alex Forencich 2025-02-16 20:46:31 -08:00
  • af912cc849 eth: Add MII PHY interface module Alex Forencich 2025-02-16 20:05:41 -08:00
  • da7fe065cc io: Rework generic ODDR implementation Alex Forencich 2025-02-16 19:27:56 -08:00
  • d01a90298c eth: Use correct clock for TX completions in MAC + FIFO testbenches Alex Forencich 2025-02-16 18:59:18 -08:00
  • 5c8037093b eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module Alex Forencich 2025-02-16 18:06:41 -08:00
  • e3d8ad8d36 io: Add source-synchronous IO modules Alex Forencich 2025-02-16 15:44:34 -08:00
  • e18a2b3457 io: Add generic IDDR and ODDR modules Alex Forencich 2025-02-16 15:41:56 -08:00
  • 51d6919622 ptp: Add timing constraints for PTP components Alex Forencich 2025-02-16 11:29:57 -08:00
  • d048a8d7c7 Update readme Alex Forencich 2025-02-13 22:23:57 -08:00
  • 9ad43f3433 Update readme Alex Forencich 2025-02-13 22:13:01 -08:00
  • fc1e0efad7 ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench Alex Forencich 2025-02-13 22:07:46 -08:00
  • ad0d44616b ptp: Add PTP TD leaf clock module and testbench Alex Forencich 2025-02-13 20:18:17 -08:00
  • 68c547b219 ptp: Minor cleanup in PTP CDC module Alex Forencich 2025-02-13 20:17:21 -08:00
  • 2eaa2f64a2 ptp: Add PTP TD PHC module and testbench Alex Forencich 2025-02-13 17:50:16 -08:00
  • 38a150b87a ptp: Add PTP period output module and testbench Alex Forencich 2025-02-13 17:06:46 -08:00
  • d1578513c8 Update readme Alex Forencich 2025-02-13 13:51:25 -08:00
  • 2abe774f8a eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench Alex Forencich 2025-02-13 13:48:54 -08:00
  • 90650aee69 eth: Add 10G Ethernet MAC module with FIFOs and testbench Alex Forencich 2025-02-13 13:47:54 -08:00
  • d76e810033 axis: Fix parameter sizing in AXI stream FIFOs Alex Forencich 2025-02-13 13:46:56 -08:00
  • f356fad6fe ptp: Add PTP clock CDC module and testbench Alex Forencich 2025-02-13 12:49:42 -08:00
  • 17b4c37a1e ptp: Add PTP clock module and testbench Alex Forencich 2025-02-13 10:52:27 -08:00
  • 8a67eaa220 eth: Clean up testbench parameters Alex Forencich 2025-02-11 22:35:18 -08:00
  • 04b73e7ddf eth: Add 1G Ethernet MAC module with FIFOs and testbench Alex Forencich 2025-02-11 22:12:57 -08:00
  • 8f8572bdee eth: Add taxi_axis_if to MAC file list files Alex Forencich 2025-02-11 15:54:15 -08:00
  • 2616e3f3e3 eth: Add 10G Ethernet combined MAC+PHY module and testbench Alex Forencich 2025-02-08 21:40:50 -08:00
  • 0ddb89b18f eth: Add 10G Ethernet MAC module and testbench Alex Forencich 2025-02-08 21:26:03 -08:00
  • fa73f9c1d5 eth: Add 1G Ethernet MAC module and testbench Alex Forencich 2025-02-08 21:25:48 -08:00
  • 8d3d703656 eth: Add MAC control modules Alex Forencich 2025-02-08 19:59:11 -08:00
  • 96e348ac84 eth: Invert TX completion output control Alex Forencich 2025-02-07 23:24:28 -08:00
  • 1c381ce22e eth: Enable tuser signals Alex Forencich 2025-02-07 22:23:03 -08:00
  • 72dabc5a9a eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench Alex Forencich 2025-02-07 18:03:23 -08:00
  • 2af4e7af3e eth: Add AXI stream 64-bit XGMII Ethernet frame transmitter module and testbench Alex Forencich 2025-02-07 18:03:15 -08:00
  • a375eb342d eth: Add AXI stream 32-bit XGMII Ethernet frame transmitter module and testbench Alex Forencich 2025-02-07 18:03:06 -08:00
  • c914adf9f1 eth: Add AXI stream GMII Ethernet frame receiver module and testbench Alex Forencich 2025-02-07 18:02:48 -08:00
  • e3f047d735 eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench Alex Forencich 2025-02-07 16:27:27 -08:00
  • f0f2a25943 eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench Alex Forencich 2025-02-07 16:25:54 -08:00
  • 8046a46680 eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench Alex Forencich 2025-02-07 16:25:06 -08:00
  • 3f501aaac9 eth: Add AXI stream GMII Ethernet frame receiver module and testbench Alex Forencich 2025-02-07 16:12:58 -08:00
  • 6da97807a7 Clean up regression-tests.yml, track disk usage Alex Forencich 2025-02-07 09:48:00 -08:00
  • d52aa2f97e axis: Add AXI stream combination async FIFO/adapter module and testbench Alex Forencich 2025-02-06 00:52:04 -08:00
  • b1dcd8c6a2 Use 20 runners for CI Alex Forencich 2025-02-06 00:48:00 -08:00
  • 69e5ae8545 axis: Add AXI stream async FIFO module and testbench Alex Forencich 2025-02-06 00:46:39 -08:00
  • a354377da9 Add scapy to tox.ini Alex Forencich 2025-02-05 21:44:27 -08:00
  • 584f2a6542 eth: Add MAC pause control modules Alex Forencich 2025-02-05 21:11:14 -08:00
  • f479a85155 lfsr: Add LFSR descrambler module and testbench Alex Forencich 2025-02-05 15:29:12 -08:00
  • e6ea90be36 lfsr: Add LFSR scrambler module and testbench Alex Forencich 2025-02-05 15:28:57 -08:00
  • aeedc3bf7d lfsr: Add LFSR PRBS checker module and testbench Alex Forencich 2025-02-05 15:28:31 -08:00
  • 328a00e30f lfsr: Add LFSR PRBS generator module and testbench Alex Forencich 2025-02-05 15:28:08 -08:00
  • fb69371974 lfsr: Add LFSR CRC computation module and testbench Alex Forencich 2025-02-05 15:27:44 -08:00
  • e35d2b2c03 eth: Add 10G PHY module and testbench Alex Forencich 2025-02-04 17:10:21 -08:00
  • c6ea4071eb eth: Add XGMII/BASE-R encode/decode modules and testbenches Alex Forencich 2025-02-04 16:14:32 -08:00
  • 8ee1f5cd18 lfsr: Add parametrizable LFSR module and testbench Alex Forencich 2025-02-04 15:39:33 -08:00
  • f0c9f69987 axis: Add COBS encoder module and testbench Alex Forencich 2025-02-04 11:49:50 -08:00
  • 215732b309 axis: Work around verilator linter bug in AXI stream FIFO Alex Forencich 2025-02-04 11:40:14 -08:00
  • 9138a7a51e axis: Add COBS decoder module and testbench Alex Forencich 2025-02-04 11:39:38 -08:00
  • 85eb59f747 axis: Add AXI stream broadcaster module and testbench Alex Forencich 2025-02-04 10:38:15 -08:00
  • beb36b78e0 io: Add switch debounce module Alex Forencich 2025-02-04 00:16:34 -08:00
  • 6ba257aa10 sync: Add signal synchronizer module Alex Forencich 2025-02-03 23:43:18 -08:00
  • 9cc4cbc670 sync: Add reset synchronizer module Alex Forencich 2025-02-03 23:42:47 -08:00
  • e23627c92f axis: Add AXI stream combined FIFO/adapter module and testbench Alex Forencich 2025-02-03 23:34:34 -08:00
  • c0a164a1d2 axis: Add AXI stream adapter module and testbench Alex Forencich 2025-02-03 23:33:29 -08:00
  • dab84912d4 Use verilator 5.032 for CI Alex Forencich 2025-02-03 23:25:18 -08:00
  • 03c0883356 axis: Add AXI stream FIFO module and testbench Alex Forencich 2025-02-03 22:43:17 -08:00
  • 06ee1beb0e axis: Add missing parameters Alex Forencich 2025-02-03 22:17:03 -08:00
  • b80187511e Configure CI to use 10 workers Alex Forencich 2025-02-03 16:39:21 -08:00
  • 7d1295bdc1 Add authors file Alex Forencich 2025-02-03 16:36:26 -08:00
  • 9590811570 axis: Add AXI stream pipeline FIFO module and testbench Alex Forencich 2025-02-03 16:35:52 -08:00
  • 47e4658b55 axis: Add AXI stream pipeline register module and testbench Alex Forencich 2025-02-03 16:35:25 -08:00
  • e155a917b9 axis: Remove extraneous parameter Alex Forencich 2025-02-03 16:29:51 -08:00
  • 3e7b842f4f Add license file Alex Forencich 2025-02-03 15:24:47 -08:00
  • d447e0e646 Add gitignore Alex Forencich 2025-02-03 15:24:38 -08:00
  • c4558a02f0 lss: Add UART module and testbench Alex Forencich 2025-02-03 15:02:48 -08:00
  • 8aa4c066b2 Update readme Alex Forencich 2025-02-03 14:22:31 -08:00
  • 3627ae13c1 Use system python for github actions CI Alex Forencich 2025-02-03 12:58:23 -08:00
  • 35a363ff55 Set up github actions Alex Forencich 2025-02-03 12:52:45 -08:00
  • 51a24481f5 Add tox configuration Alex Forencich 2025-02-03 12:49:57 -08:00
  • c7f719b435 axis: Add AXI stream register module and testbench Alex Forencich 2025-02-03 12:49:08 -08:00
  • e1233eaffe axis: Add SV interface for AXI stream Alex Forencich 2025-02-02 22:45:12 -08:00
  • 5f87c2e84e Initial commit Alex Forencich 2025-02-02 22:45:06 -08:00