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• b8021192e3 lss: Clean up I2C testbenches Alex Forencich 2025-03-19 14:52:26 -07:00
• 79e0bf6976 lss: Remove redundant tristate control outputs on I2C modules Alex Forencich 2025-03-19 12:41:39 -07:00
• fa2385aedb lss: Add I2C single register module and testbench Alex Forencich 2025-03-19 12:15:47 -07:00
• 44c811f82a lss: Add I2C master module and testbench Alex Forencich 2025-03-19 10:41:16 -07:00
• 1e3e298d9e Add cocotbext-i2c to tox.ini Alex Forencich 2025-03-19 10:18:03 -07:00
• a86f858116 docs: Add readthedocs yaml file Alex Forencich 2025-03-18 16:23:30 -07:00
• 115bacae02 docs: Add sphinx infrastructure Alex Forencich 2025-03-18 16:12:49 -07:00
• 3624976f0e hip: Add support for optional phase shifter clock to fractional MMCM module Alex Forencich 2025-03-17 21:05:49 -07:00
• d7e29a2b5c hip: Add support for optional cascaded MMCM for offset clock Alex Forencich 2025-03-17 21:04:52 -07:00
• b468d92e39 hip: Report error if fractional MMCM configuration does not work Alex Forencich 2025-03-17 21:00:12 -07:00
• eacae099bf hip: Add fractional MMCM wrapper for generating offset clocks for DDMTD Alex Forencich 2025-03-13 21:00:09 -07:00
• ebeadee172 lss: Implement fractional baud rate generation for UART Alex Forencich 2025-03-11 23:49:39 -07:00
• 1c686391ab lss: Refactor UART module to split out and share baud rate generation logic Alex Forencich 2025-03-11 23:09:19 -07:00
• 7df14e54e5 xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections Alex Forencich 2025-03-11 18:33:57 -07:00
• 8d4ad59727 Update readme Alex Forencich 2025-03-10 17:04:03 -07:00
• 15653923fd xfcp: Add XFCP switch module and testbench Alex Forencich 2025-03-10 15:30:59 -07:00
• 0ee729b744 xfcp: Add XFCP AXI module and testbench Alex Forencich 2025-03-10 13:28:05 -07:00
• 70d77c8a95 xfcp: Add XFCP AXI lite module and testbench Alex Forencich 2025-03-10 13:25:55 -07:00
• ed9e8ffab3 eth: Use unpacked arrays for multidimensional ports Alex Forencich 2025-03-07 11:05:58 -08:00
• 6e4988f010 eth: Fix PFC/LFC tests for 10G MAC+PHY Alex Forencich 2025-03-07 10:41:49 -08:00
• cb04b84e18 example/VCU118: Add example design for VCU118 Alex Forencich 2025-03-07 00:29:17 -08:00
• 024353c68a lss: Add MDIO master Alex Forencich 2025-03-06 23:48:57 -08:00
• ed325acb1e axis: Implement tstrb in pipeline FIFO Alex Forencich 2025-03-06 16:18:20 -08:00
• e9ac4947ba axis: Normalize unpacked dimension Alex Forencich 2025-03-06 16:17:05 -08:00
• 56215865da axi: Normalize unpacked dimension Alex Forencich 2025-03-06 16:16:29 -08:00
• c422297666 axis: Tie off unused sideband signals in COBS encoder Alex Forencich 2025-03-06 16:11:38 -08:00
• 194a686bda xfcp: Add XFCP UART interface module and testbench Alex Forencich 2025-03-04 22:05:11 -08:00
• 98ea651532 axis: Use unpacked arrays for unpacking interface signals Alex Forencich 2025-02-28 23:24:56 -08:00
• 56a3c9f1ba axis: Add AXI stream arbitrated multiplexer module and testbench Alex Forencich 2025-02-28 23:24:40 -08:00
• 46e60d32f2 prim: Add arbiter module and testbench Alex Forencich 2025-02-28 21:04:49 -08:00
• 5966d05740 prim: Add priority encoder and testbench Alex Forencich 2025-02-28 21:04:32 -08:00
• a790e270b8 axi: Replace reg with logic in AXI lite RAM Alex Forencich 2025-02-27 13:44:18 -08:00
• df300b7dad axis: Add AXI stream multiplexer module and testbench Alex Forencich 2025-02-27 13:28:02 -08:00
• aa9900de94 axi: Add STRB parameters to testbenches Alex Forencich 2025-02-27 10:06:56 -08:00
• ff2e3c1331 Update readme Alex Forencich 2025-02-27 00:59:30 -08:00
• ad3042e090 axi: Add AXI lite dual-port RAM module and testbench Alex Forencich 2025-02-27 00:58:30 -08:00
• 55c097f47d axi: Add AXI RAM module and testbench Alex Forencich 2025-02-27 00:27:11 -08:00
• 0632b1982e axi: Add AXI lite RAM module and testbench Alex Forencich 2025-02-27 00:26:03 -08:00
• c478f187b1 Update readme Alex Forencich 2025-02-26 21:09:29 -08:00
• ae26b61200 axi: Add AXI register module and testbench Alex Forencich 2025-02-26 21:08:39 -08:00
• 1075896ecc axi: Add AXI lite register module and testbench Alex Forencich 2025-02-26 21:02:50 -08:00
• 5e5bce9aa0 axi: Add SV interface for AXI Alex Forencich 2025-02-26 20:51:25 -08:00
• 5f9f71e615 axi: Add SV interface for AXI lite Alex Forencich 2025-02-26 20:51:16 -08:00
• f419b3167a axis: Switch AXI stream interface license to MIT Alex Forencich 2025-02-26 20:50:40 -08:00
• da3996cf5c example/ADM_PCIE_9V3: Example design cleanup Alex Forencich 2025-02-26 14:16:18 -08:00
• c6cbb57fe7 lss: Extract UART data width setting from interface Alex Forencich 2025-02-26 14:15:42 -08:00
• 07d75f231a eth: Fix testbenches Alex Forencich 2025-02-25 17:35:09 -08:00
• 01f836a2f9 example/KR260: Remove drive strength settings from input pins Alex Forencich 2025-02-25 17:18:08 -08:00
• cf44abae0d axis: Use signal sync module for async FIFO output pause Alex Forencich 2025-02-25 17:13:10 -08:00
• 181691941f eth: Use signal sync module for RGMII MAC speed detection Alex Forencich 2025-02-25 17:12:50 -08:00
• f8d5d6a45e eth: Use signal sync module for GMII MAC speed detection Alex Forencich 2025-02-25 17:12:10 -08:00
• 64c1cb1e39 eth: Use signal sync module for internal MAC pause handling Alex Forencich 2025-02-25 16:27:37 -08:00
• 84fb93b5c3 example: Add signal sync timing constraints to example designs Alex Forencich 2025-02-25 16:04:32 -08:00
• 8785c1517b example/fb2CG: Add example design for fb2CG@KU15P Alex Forencich 2025-02-25 15:49:21 -08:00
• 5a8ac23922 io: Add LED shift register driver module Alex Forencich 2025-02-25 15:44:57 -08:00
• 6e90f4f0a0 syn: Add timing constraints for signal synchronizer Alex Forencich 2025-02-25 15:39:00 -08:00
• eae85cb8c7 syn: Clean up timing constraints for reset sync Alex Forencich 2025-02-25 15:38:39 -08:00
• d0c7d7735a example/Nexus_K3P_Q: Reorganize MAC instances Alex Forencich 2025-02-25 12:20:01 -08:00
• abb0ca1bcc example/ADM_PCIE_9V3: Reorganize MAC instances Alex Forencich 2025-02-25 12:01:20 -08:00
• b18b643eed example/Alveo: Add example design for Xilinx Alveo series Alex Forencich 2025-02-25 11:34:26 -08:00
• 4cdc4be47e example/ADM_PCIE_9V3: Testbench cleanup Alex Forencich 2025-02-24 21:42:23 -08:00
• ffe667b047 example/Nexus_K3P_Q: Add example design for Cisco Nexus K3P-Q Alex Forencich 2025-02-24 21:39:26 -08:00
• 8ffbd43e08 example/Nexus_K3P_S: Add example design for Cisco Nexus K35-S/K3P-S Alex Forencich 2025-02-24 21:04:42 -08:00
• 916355ca8a eth: Add TX/RX polarity control to MAC+PHY+GT wrapper Alex Forencich 2025-02-24 17:17:23 -08:00
• 7047cb5c4f eth: Tie off transceiver control signals during simulation Alex Forencich 2025-02-24 16:28:59 -08:00
• 34266fe25d example/ZCU111: Add example design for ZCU111 Alex Forencich 2025-02-23 17:32:21 -08:00
• 27033384d9 example: Update GPIO constraints Alex Forencich 2025-02-23 16:24:15 -08:00
• 2fa899373e Update readme Alex Forencich 2025-02-23 14:13:42 -08:00
• f424eb3f98 example/ADM-PCIE-9V3: Clean up makefiles Alex Forencich 2025-02-23 14:13:17 -08:00
• aedf4d5c4c example/ZCU106: Fix width Alex Forencich 2025-02-23 14:12:57 -08:00
• d2f6a94318 example/ZCU102: Add example design for ZCU102 Alex Forencich 2025-02-23 14:12:34 -08:00
• 87b696b2aa example/ZCU106: Add example design for ZCU106 Alex Forencich 2025-02-23 12:12:28 -08:00
• 182b44f7bc example/KCU105: Tie correct signals high Alex Forencich 2025-02-23 12:06:30 -08:00
• 951f81680a example/ADM_PCIE_9V3: Add example design for ADM-PCIE-9V3 Alex Forencich 2025-02-23 00:49:41 -08:00
• 9a8f311f2c example/KR160: Use correct MMCM primitive Alex Forencich 2025-02-23 00:36:13 -08:00
• 75a746333e Update readme Alex Forencich 2025-02-22 23:36:13 -08:00
• b6be624bdb example/KCU105: Add support for 10GBASE-R on KCU105 Alex Forencich 2025-02-22 23:15:24 -08:00
• 4a439783f1 example/KR260: Add support for 10GBASE-R on KR260 Alex Forencich 2025-02-22 23:01:52 -08:00
• db8b1fc27e example/VCU108: Add 25G MACs on QSFP28 port on VCU108 Alex Forencich 2025-02-22 22:33:54 -08:00
• f0ec82a384 eth: Add MAC+PHY+GT wrapper for UltraScale Alex Forencich 2025-02-22 22:22:54 -08:00
• 7613cae4f0 eth: Use 2D array for PFC config Alex Forencich 2025-02-22 22:08:43 -08:00
• 7f2ecf9b49 eth: Implement RX sequence error reporting in MAC+PHY module Alex Forencich 2025-02-22 10:16:32 -08:00
• 422c54229e eth: Split block type checks in MAC+PHY to reduce fanin Alex Forencich 2025-02-22 10:02:08 -08:00
• 8f6a99112b eth: Add missing block types to MAC+PHY logic Alex Forencich 2025-02-22 09:55:28 -08:00
• 6a294cef2c Use string type for string parameters Alex Forencich 2025-02-21 19:14:28 -08:00
• 6154506c0a axis: Use reset synchronizer module in AXI stream async FIFO Alex Forencich 2025-02-20 12:44:23 -08:00
• 17f3613ca4 eth: Clean up function definitions Alex Forencich 2025-02-20 12:21:33 -08:00
• e388cb22c6 example/KR260: Update readme Alex Forencich 2025-02-20 10:21:49 -08:00
• 650da9c972 example/HTG940: Add example design for HTG940 Alex Forencich 2025-02-20 10:20:15 -08:00
• 152b5aeed5 example/KC705: Update readme Alex Forencich 2025-02-19 13:24:31 -08:00
• 4db3ee5cd5 example/KR260: Update readme Alex Forencich 2025-02-19 12:03:53 -08:00
• a56a33abc9 examples: Add notes on required licenses Alex Forencich 2025-02-19 12:02:07 -08:00
• d5ed74431a example/KR260: Add example design for KR260 Alex Forencich 2025-02-19 10:59:15 -08:00
• ae6f22e4da example/KCU105: Fix MMCM config Alex Forencich 2025-02-18 20:10:25 -08:00
• 8241f33d47 example/VCU108: Example design cleanup Alex Forencich 2025-02-18 18:13:10 -08:00
• a4025a1ead example/KC705: Example design cleanup Alex Forencich 2025-02-18 18:12:54 -08:00
• 2e35f5b5ff example/KCU105: Add example design for KCU105 Alex Forencich 2025-02-18 18:08:25 -08:00
• c7b79f9afb example/VCU108: Add example design for VCU108 Alex Forencich 2025-02-18 15:14:36 -08:00
• daa5ca38af example/KC705: Fix MMCM notes Alex Forencich 2025-02-18 14:26:22 -08:00
• 53688afeb5 example/KC705: Add example design for Xilinx KC705 Alex Forencich 2025-02-18 09:45:36 -08:00