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  • 38ae0c1587 eth: Clean up casts Alex Forencich 2025-09-07 15:18:23 -07:00
  • 9307e0df6c pcie: Clean up casts Alex Forencich 2025-09-07 15:17:46 -07:00
  • 1e12094f45 stats: Clean up casts Alex Forencich 2025-09-07 14:58:16 -07:00
  • 32ed95893c dma: Clean up casts in DMA PSDPRAM model Alex Forencich 2025-09-07 14:37:41 -07:00
  • e42a2dd8b4 lss: Use cocotb.start_soon instead of cocotb.fork Alex Forencich 2025-09-07 14:36:27 -07:00
  • 6a5faf9ebf Cast to int instead of using .integer Alex Forencich 2025-09-07 11:25:34 -07:00
  • 40908b1b92 Testbench cleanup for cocotb 2.0 Alex Forencich 2025-09-07 10:59:38 -07:00
  • 884fe1a006 apb: Add lib symlink Alex Forencich 2025-09-06 16:50:44 -07:00
  • 81a918d223 apb: Add SV interface for APB Alex Forencich 2025-09-06 16:50:38 -07:00
  • 20f14ace97 Update readme Alex Forencich 2025-09-06 07:06:50 -07:00
  • 553dea534e eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2 Alex Forencich 2025-09-06 07:03:35 -07:00
  • 0d7e0cf590 eth/example/ZCU111: Clean up RFDC clocking Alex Forencich 2025-09-05 07:30:30 -07:00
  • 6c9026bccf eth/example/HTG9200: Fix refclock frequency in testbench Alex Forencich 2025-09-05 07:15:26 -07:00
  • 2ae5b5fae3 pcie: Remove TLP_HDR_W parameter from testbenches Alex Forencich 2025-09-01 22:08:18 -07:00
  • cdfb1566f5 Update readme Alex Forencich 2025-08-31 21:38:06 -07:00
  • a6db298eeb dma: Add async DMA PSDPRAM module and testbench Alex Forencich 2025-08-31 21:30:25 -07:00
  • 48da5315fe dma: Add DMA PSDPRAM module and testbench Alex Forencich 2025-08-31 21:29:55 -07:00
  • d57b49b29c dma: Add PSDPRAM simulation model Alex Forencich 2025-08-31 21:05:20 -07:00
  • c5fea4d920 dma: Add lib symlink Alex Forencich 2025-08-31 21:04:44 -07:00
  • 10500e6c6c dma: Add DMA RAM interface Alex Forencich 2025-08-31 21:04:22 -07:00
  • e87e16c299 axi: Add AXI FIFO module and testbench Alex Forencich 2025-08-30 22:17:53 -07:00
  • 0080125120 axi: Add AXI to AXI lite adapter module and testbench Alex Forencich 2025-08-30 21:11:20 -07:00
  • 94a821192c axi: Add AXI width converter module and testbench Alex Forencich 2025-08-30 21:10:08 -07:00
  • 5f6487964e axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface Alex Forencich 2025-08-30 13:55:33 -07:00
  • e43d6acbbd axi: Add AXI lite to AXI adapter module and testbench Alex Forencich 2025-08-30 13:40:43 -07:00
  • c22e659259 axi: Add AXI lite width converter module and testbench Alex Forencich 2025-08-30 13:02:27 -07:00
  • 4dd84efd6c Update readme Alex Forencich 2025-08-29 18:00:22 -07:00
  • bf584147a1 pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master Alex Forencich 2025-08-29 17:59:56 -07:00
  • b3441f6408 pcie: Rename enable to en in PCIe US AXI lite master Alex Forencich 2025-08-29 17:59:33 -07:00
  • 63c961cab4 pcie: Fix some corner cases in PCIe US AXI lite master Alex Forencich 2025-08-29 16:50:31 -07:00
  • b5c9c02b03 pcie: Add UltraScale PCIe AXI Lite Master module and testbench Alex Forencich 2025-08-25 22:39:28 -07:00
  • 06e6f3e1b4 lss: Optimize delay implementation in I2C master module Alex Forencich 2025-08-24 11:30:03 -07:00
  • c2c4f5316d xfcp: Fix width Alex Forencich 2025-08-24 11:26:25 -07:00
  • 07ae2ba989 eth: Add RFDC to ZCU111 example design Alex Forencich 2025-08-24 11:26:14 -07:00
  • 4c43b68f94 eth: Add 6QSFP FMC support to HTG9200 example design Alex Forencich 2025-08-20 16:24:39 -07:00
  • cf0ec74849 eth: HTG9200 example design cleanup Alex Forencich 2025-08-20 06:37:14 -07:00
  • 5e890bc6cd axis: Add AXI stream tie and null source/sink modules Alex Forencich 2025-08-20 06:33:21 -07:00
  • a8dbe26f12 zircon: tdest not used on TX path after length/checksum computation, which also extracts the tdest value Alex Forencich 2025-08-15 13:36:14 -07:00
  • 3a07e3e28c zircon: Improve sideband signal handling in length/checksum computation module Alex Forencich 2025-08-15 13:34:15 -07:00
  • d0efd5f24c zircon: Connect tdest Alex Forencich 2025-08-14 14:11:55 -07:00
  • 9955b79fcd zircon: Add FIFO configuration parameters Alex Forencich 2025-08-13 17:17:34 -07:00
  • af8daa89ce zircon: Fix flow control bug in parser Alex Forencich 2025-08-13 13:44:49 -07:00
  • 0aad8ef2cc zircon: Fix testbench Alex Forencich 2025-08-06 15:33:05 -07:00
  • e5ce27cc30 zircon: Add lib symlink Alex Forencich 2025-08-06 15:13:47 -07:00
  • 67bfb947f4 zircon: Add TX buffer module Alex Forencich 2025-08-06 15:09:04 -07:00
  • 18fdf53d5d zircon: Add ingress and egress modules Alex Forencich 2025-08-06 15:08:40 -07:00
  • 48465423fb zircon: Add length and checksum computation module and testbench Alex Forencich 2025-08-06 15:06:12 -07:00
  • 7c1f2652b6 zircon: Add TX deparser module and testbench Alex Forencich 2025-08-06 14:57:14 -07:00
  • babce69bd0 zircon: Add RX parser module and testbench Alex Forencich 2025-08-06 14:49:22 -07:00
  • 65cb6124c4 Update readme Alex Forencich 2025-08-02 21:20:34 -07:00
  • a16a667f81 lss: Add I2C init module Alex Forencich 2025-08-02 21:20:21 -07:00
  • d4089096ae example: Add example design for HTG-9200 Alex Forencich 2025-08-02 21:19:58 -07:00
  • 467b044e88 lss: Add missing file list file handling Alex Forencich 2025-08-02 15:15:29 -07:00
  • 89f60f26ff lss: Add some interface configuration checks to I2C modules Alex Forencich 2025-08-02 14:40:56 -07:00
  • 8017534c45 lss: Rename I2C data ports to reduce ambiguity Alex Forencich 2025-08-02 14:40:33 -07:00
  • 4620370035 lss: Add I2C slave AXI lite master module and testbench Alex Forencich 2025-08-02 00:44:14 -07:00
  • 37825a02f4 lss: Add I2C slave module and testbench Alex Forencich 2025-08-02 00:22:11 -07:00
  • 8bcd7ca037 axis: Expand size range for concatenator module tests Alex Forencich 2025-07-31 14:13:13 -07:00
  • 933899887a axis: Add AXI stream switch module and testbench Alex Forencich 2025-07-31 11:47:49 -07:00
  • dd8b2a89ed axis: Remove unnecessary idle cycles in taxi_axis_concat Alex Forencich 2025-07-30 22:03:16 -07:00
  • bd0b0cd75a Update documentation URL Alex Forencich 2025-07-30 19:12:45 -07:00
  • d10e3cf5c0 axis: Add AXI stream demultiplexer module and testbench Alex Forencich 2025-07-30 19:10:48 -07:00
  • b266aa2949 axis: Add AXI stream concatenator module and testbench Alex Forencich 2025-07-30 18:57:11 -07:00
  • 059c7cd5ce axis: Minor cleanup in taxi_axis_mux Alex Forencich 2025-07-29 09:43:11 -07:00
  • 75a8750679 axis: Minor cleanup in taxi_axis_arb_mux Alex Forencich 2025-07-29 09:40:03 -07:00
  • 2065151c01 eth: Update 10G-only example designs to use 32-bit MACs Alex Forencich 2025-06-17 23:19:30 -07:00
  • 7031a3f0b1 eth: Add 32-bit mode tests for UltraScale wrapper Alex Forencich 2025-06-17 22:19:55 -07:00
  • 5b0cae2aac eth: Add 32-bit support to combined MAC+PCS module Alex Forencich 2025-06-17 21:37:34 -07:00
  • 7b1ae24d95 eth: Report framing and bad block errors in 32-bit BASE-R RX module Alex Forencich 2025-06-17 21:34:42 -07:00
  • fd521a1511 eth: Avoid hardcoding clock period Alex Forencich 2025-06-17 20:15:50 -07:00
  • 295dc2dd23 eth: Add 32-bit AXI stream BASE-R RX module and testbench Alex Forencich 2025-06-17 20:15:09 -07:00
  • ebb8bf0bd4 eth: Add 32-bit AXI stream BASE-R TX module and testbench Alex Forencich 2025-06-17 20:14:30 -07:00
  • 6f5adb1b41 eth: Reset pack_seq even if the header is not marked as valid Alex Forencich 2025-06-17 16:32:48 -07:00
  • e8cea4c860 eth: Use for loop to reduce duplication Alex Forencich 2025-06-17 11:50:29 -07:00
  • facdc5fe68 eth: Remove extraneous constants Alex Forencich 2025-06-16 16:01:12 -07:00
  • 17e48c5f51 eth: Support 32-bit mode in UltraScale wrapper Alex Forencich 2025-06-15 13:16:58 -07:00
  • 6407b4c7f0 eth: Support 32-bit sync gearbox in 10G MAC Alex Forencich 2025-06-15 13:11:26 -07:00
  • ab09ceb891 eth: Support 32 bit mode in BASE-R PHY Alex Forencich 2025-06-15 13:00:14 -07:00
  • e6b5cd6ecd eth: Support 32 bit mode in BASE-R model Alex Forencich 2025-06-15 12:56:03 -07:00
  • 70c0e3d52a eth: Fix RX BER monitor when gearbox is enabled Alex Forencich 2025-06-15 12:54:01 -07:00
  • 2e1619a045 eth: Connect and tie off txsequence Alex Forencich 2025-06-15 01:20:23 -07:00
  • cc8ec558bf eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules Alex Forencich 2025-06-14 22:54:09 -07:00
  • e993a6cfbf eth: Cleanup Alex Forencich 2025-06-13 19:38:06 -07:00
  • 65eef8b5e8 eth: Parameter cleanup Alex Forencich 2025-06-13 19:28:21 -07:00
  • eae4d67367 eth: Fix testbenches Alex Forencich 2025-06-13 17:57:57 -07:00
  • f9041cd9d2 eth: Fix multidriven net Alex Forencich 2025-06-13 16:51:07 -07:00
  • 280e5129b8 example: Build all MAC variants for ZCU106 Alex Forencich 2025-06-13 16:48:22 -07:00
  • 3349561810 eth: Remove extraneous defaults Alex Forencich 2025-06-13 16:45:00 -07:00
  • 741615f203 eth: Fix parameter name Alex Forencich 2025-06-13 16:40:32 -07:00
  • e846e7f0cd eth: Add gearbox support to 64-bit 10G MAC Alex Forencich 2025-06-13 16:39:55 -07:00
  • 28195390a2 eth: Add GBX_CNT to taxi_xgmii_baser_enc_64 testbench Alex Forencich 2025-06-13 16:35:04 -07:00
  • d4acf48e0a eth: Fix gearbox interface in 10G PHY Alex Forencich 2025-06-13 16:34:44 -07:00
  • 0fd4000f69 eth: Support both split and combined MAC/PCS in UltraScale wrapper Alex Forencich 2025-06-13 14:31:14 -07:00
  • 886aa65522 eth: Add testbench for taxi_eth_mac_25g_us module Alex Forencich 2025-06-13 10:34:43 -07:00
  • 98d06954cc eth: Avoid hardcoding clock period Alex Forencich 2025-06-13 10:28:53 -07:00
  • 4e66dd0f98 eth: Rename gearbox start signals to sync Alex Forencich 2025-06-12 15:45:07 -07:00
  • ca3ee2d197 eth: Fix PFC/LFC parameters in 25G MAC modules Alex Forencich 2025-06-12 14:56:55 -07:00
  • a146aeaf21 lfsr: Merge output state with data when possible Alex Forencich 2025-06-11 18:48:07 -07:00
  • faa914c828 lfsr: Merge input state with data when possible Alex Forencich 2025-06-11 18:30:31 -07:00
  • a4ac9e7bb0 lfsr: Add PCIe scramlber sequence as a galois-mode PRBS test Alex Forencich 2025-06-11 13:06:51 -07:00