mirror of
https://github.com/fpganinja/taxi.git
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eth: Add support for 1000BASE-X autonegotiation to 1000BASE-X PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -1,3 +1,5 @@
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taxi_eth_phy_1g_basex.sv
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taxi_eth_phy_1g_basex_rx.f
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taxi_eth_phy_1g_basex_tx.f
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taxi_eth_phy_1g_basex_an.sv
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../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
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@@ -21,6 +21,7 @@ module taxi_eth_phy_1g_basex #
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parameter CTRL_W = (DATA_W/8),
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parameter logic TX_GBX_IF_EN = 1'b0,
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parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
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parameter logic AN_EN = 1'b1,
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parameter logic BIT_REVERSE = 1'b0,
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parameter logic ENC_8B10B_EN = 1'b0,
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parameter logic DEC_8B10B_EN = ENC_8B10B_EN,
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@@ -66,6 +67,17 @@ module taxi_eth_phy_1g_basex #
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input wire logic serdes_rx_data_valid = 1'b1,
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output wire logic serdes_rx_reset_req,
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/*
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* Autonegotiation
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*/
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input wire logic an_en = 1'b1,
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input wire logic an_restart = 1'b0,
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input wire logic an_speedup = 1'b0,
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output wire logic an_intr,
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output wire logic an_complete,
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input wire logic [15:0] an_adv_ability = 16'h0020,
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output wire logic [15:0] an_lp_adv_ability,
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/*
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* Status
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*/
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@@ -83,10 +95,97 @@ module taxi_eth_phy_1g_basex #
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input wire logic cfg_rx_prbs31_enable = 1'b0
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);
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// Autonegotiation
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wire logic [15:0] rx_an_cfg;
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wire logic rx_an_cfg_valid;
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wire logic rx_an_ability_match;
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wire logic rx_an_ack_match;
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wire logic rx_an_idle_match;
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wire logic [15:0] tx_an_cfg;
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wire logic tx_an_cfg_valid;
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wire logic tx_an_cfg_ready;
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if (AN_EN) begin : an
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// synchronize RX signals to TX
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wire [15:0] sync_rx_an_cfg;
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wire sync_rx_an_cfg_valid;
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wire sync_rx_an_ability_match;
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wire sync_rx_an_ack_match;
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wire sync_rx_an_idle_match;
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taxi_sync_signal #(
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.WIDTH(16+4),
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.N(2)
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)
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sync_inst (
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.clk(tx_clk),
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.in({
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rx_an_cfg,
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rx_an_cfg_valid,
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rx_an_ability_match,
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rx_an_ack_match,
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rx_an_idle_match
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}),
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.out({
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sync_rx_an_cfg,
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sync_rx_an_cfg_valid,
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sync_rx_an_ability_match,
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sync_rx_an_ack_match,
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sync_rx_an_idle_match
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})
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);
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taxi_eth_phy_1g_basex_an #(
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.DATA_W(DATA_W)
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)
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an_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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/*
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* AN config register
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*/
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.rx_an_cfg(sync_rx_an_cfg),
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.rx_an_cfg_valid(sync_rx_an_cfg_valid),
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.rx_an_ability_match(sync_rx_an_ability_match),
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.rx_an_ack_match(sync_rx_an_ack_match),
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.rx_an_idle_match(sync_rx_an_idle_match),
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.tx_an_cfg(tx_an_cfg),
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.tx_an_cfg_valid(tx_an_cfg_valid),
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.tx_an_cfg_ready(tx_an_cfg_ready),
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/*
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* Autonegotiation
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*/
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.an_en(an_en),
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.an_restart(an_restart),
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.an_speedup(an_speedup),
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.an_intr(an_intr),
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.an_complete(an_complete),
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.an_adv_ability(an_adv_ability),
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.an_lp_adv_ability(an_lp_adv_ability)
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);
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end else begin : an
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assign tx_an_cfg = '0;
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assign tx_an_cfg_valid = 1'b0;
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assign an_intr = 1'b0;
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assign an_complete = 1'b0;
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assign an_lp_adv_ability = '0;
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end
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taxi_eth_phy_1g_basex_rx #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.GBX_IF_EN(RX_GBX_IF_EN),
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.AN_EN(AN_EN),
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.BIT_REVERSE(BIT_REVERSE),
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.DEC_8B10B_EN(DEC_8B10B_EN),
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.PRBS31_EN(PRBS31_EN),
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@@ -113,6 +212,15 @@ rx_inst (
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.serdes_rx_data_valid(serdes_rx_data_valid),
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.serdes_rx_reset_req(serdes_rx_reset_req),
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/*
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* AN config register
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*/
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.rx_an_cfg(rx_an_cfg),
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.rx_an_cfg_valid(rx_an_cfg_valid),
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.rx_an_ability_match(rx_an_ability_match),
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.rx_an_ack_match(rx_an_ack_match),
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.rx_an_idle_match(rx_an_idle_match),
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/*
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* Status
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*/
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@@ -133,6 +241,7 @@ taxi_eth_phy_1g_basex_tx #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.GBX_IF_EN(TX_GBX_IF_EN),
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.AN_EN(AN_EN),
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.BIT_REVERSE(BIT_REVERSE),
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.ENC_8B10B_EN(ENC_8B10B_EN),
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.PRBS31_EN(PRBS31_EN),
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@@ -165,6 +274,13 @@ tx_inst (
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.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
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.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
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/*
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* AN config register
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*/
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.tx_an_cfg(tx_an_cfg),
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.tx_an_cfg_valid(tx_an_cfg_valid),
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.tx_an_cfg_ready(tx_an_cfg_ready),
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/*
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* Configuration
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*/
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256
src/eth/rtl/taxi_eth_phy_1g_basex_an.sv
Normal file
256
src/eth/rtl/taxi_eth_phy_1g_basex_an.sv
Normal file
@@ -0,0 +1,256 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 1000BASE-X Ethernet PHY autonegotiation
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*/
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module taxi_eth_phy_1g_basex_an #
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(
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parameter DATA_W = 16
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AN config register
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*/
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input wire logic [15:0] rx_an_cfg,
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input wire logic rx_an_cfg_valid,
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input wire logic rx_an_ability_match,
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input wire logic rx_an_ack_match,
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input wire logic rx_an_idle_match,
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output wire logic [15:0] tx_an_cfg,
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output wire logic tx_an_cfg_valid,
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input wire logic tx_an_cfg_ready,
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/*
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* Autonegotiation
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*/
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input wire logic an_en = 1'b1,
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input wire logic an_restart = 1'b0,
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input wire logic an_speedup = 1'b0,
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output wire logic an_intr,
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output wire logic an_complete,
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input wire logic [15:0] an_adv_ability = 16'h0020,
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output wire logic [15:0] an_lp_adv_ability
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);
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localparam logic [15:0] AN_ACK = 16'h4000;
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localparam logic [15:0] AN_NP = 16'h8000;
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typedef enum logic [2:0] {
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STATE_START,
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STATE_AN_RESTART,
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STATE_ABILITY_DET,
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STATE_ACK_DET,
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STATE_ACK_CPL,
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STATE_IDLE_DET,
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STATE_DONE
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} state_t;
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state_t state_reg = STATE_START, state_next;
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logic [20:0] delay_count_reg = '0, delay_count_next;
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logic delay_run_reg = 1'b0, delay_run_next;
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logic [15:0] tx_an_cfg_reg = '0, tx_an_cfg_next;
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logic tx_an_cfg_valid_reg = 1'b0, tx_an_cfg_valid_next;
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logic an_intr_reg = 1'b0, an_intr_next;
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logic an_complete_reg = 1'b0, an_complete_next;
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logic [15:0] an_lp_adv_ability_reg = '0, an_lp_adv_ability_next;
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assign tx_an_cfg = tx_an_cfg_reg;
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assign tx_an_cfg_valid = tx_an_cfg_valid_reg;
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assign an_intr = an_intr_reg;
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assign an_complete = an_complete_reg;
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assign an_lp_adv_ability = an_lp_adv_ability_reg;
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always_comb begin
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state_next = STATE_START;
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delay_count_next = delay_count_reg;
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delay_run_next = delay_run_reg;
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tx_an_cfg_next = tx_an_cfg_reg;
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tx_an_cfg_valid_next = tx_an_cfg_valid_reg && !tx_an_cfg_ready;
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an_intr_next = 1'b0;
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an_complete_next = an_complete_reg;
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an_lp_adv_ability_next = an_lp_adv_ability_reg;
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if (delay_run_reg) begin
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if (delay_count_reg != 0) begin
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delay_count_next = delay_count_reg - 1;
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end else begin
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delay_run_next = 1'b0;
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end
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end else begin
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// 10 ms timer
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if (DATA_W == 16) begin
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delay_count_next = an_speedup ? 625 : 625000;
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end else begin
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delay_count_next = an_speedup ? 1250 : 1250000;
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end
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end
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case (state_reg)
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STATE_START: begin
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// start
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an_complete_next = 1'b0;
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tx_an_cfg_next = '0;
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if (an_en) begin
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tx_an_cfg_valid_next = 1'b1;
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if (delay_run_reg) begin
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// restart link timer
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delay_run_next = 1'b0;
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state_next = STATE_START;
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end else begin
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// AN restart state
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delay_run_next = 1'b1;
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state_next = STATE_AN_RESTART;
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end
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end else begin
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// AN disabled
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state_next = STATE_START;
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end
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end
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STATE_AN_RESTART: begin
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// AN restart - send zeroed config reg to trigger link partner to restart the AN process
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tx_an_cfg_next = '0;
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tx_an_cfg_valid_next = 1'b1;
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if (!delay_run_reg) begin
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// link timer expired
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state_next = STATE_ABILITY_DET;
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end else begin
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state_next = STATE_AN_RESTART;
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end
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end
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STATE_ABILITY_DET: begin
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// ability detect state - transfer AN ability value with ACK clear
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tx_an_cfg_next = an_adv_ability & ~AN_ACK;
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tx_an_cfg_valid_next = 1'b1;
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if (rx_an_ability_match && rx_an_cfg != 0) begin
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// got ability advertisement from link partner
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an_lp_adv_ability_next = rx_an_cfg;
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state_next = STATE_ACK_DET;
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end else begin
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state_next = STATE_ABILITY_DET;
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end
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end
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STATE_ACK_DET: begin
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// acknowledge detect - wait for ACK from link partner
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tx_an_cfg_next = an_adv_ability | AN_ACK;
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tx_an_cfg_valid_next = 1'b1;
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if (rx_an_ability_match && rx_an_cfg == 0) begin
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// restart request from link partner
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state_next = STATE_START;
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end else if (rx_an_ack_match) begin
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// acknowledge match
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an_lp_adv_ability_next = rx_an_cfg;
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if (rx_an_cfg == (an_lp_adv_ability_reg | AN_ACK)) begin
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// consistent with previously-seen value
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delay_run_next = 1'b1;
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state_next = STATE_ACK_CPL;
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end else begin
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// inconsistent, restart AN
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state_next = STATE_START;
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end
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end else begin
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state_next = STATE_ACK_DET;
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end
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end
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STATE_ACK_CPL: begin
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// complete acknowledge - give link partner time to detect our ACK
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tx_an_cfg_next = an_adv_ability | AN_ACK;
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tx_an_cfg_valid_next = 1'b1;
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if (rx_an_ability_match && rx_an_cfg == 0) begin
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// restart request from link partner
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state_next = STATE_START;
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end else if (!delay_run_reg) begin
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// link timer expired
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delay_run_next = 1'b1;
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state_next = STATE_IDLE_DET;
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end else begin
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state_next = STATE_ACK_CPL;
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end
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end
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STATE_IDLE_DET: begin
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if (rx_an_ability_match && rx_an_cfg == 0) begin
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// restart request from link partner
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state_next = STATE_START;
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end else if (rx_an_idle_match && !delay_run_reg) begin
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// idle match and link timer expired
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an_complete_next = 1'b1;
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state_next = STATE_DONE;
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end else begin
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state_next = STATE_IDLE_DET;
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end
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end
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STATE_DONE: begin
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if (rx_an_ability_match && rx_an_cfg == 0) begin
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// restart request from link partner
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state_next = STATE_START;
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end else begin
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state_next = STATE_DONE;
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end
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end
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default: begin
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state_next = STATE_START;
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end
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endcase
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if (!an_en || an_restart) begin
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state_next = STATE_START;
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end
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end
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always @(posedge clk) begin
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state_reg <= state_next;
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delay_count_reg <= delay_count_next;
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delay_run_reg <= delay_run_next;
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tx_an_cfg_reg <= tx_an_cfg_next;
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tx_an_cfg_valid_reg <= tx_an_cfg_valid_next;
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an_intr_reg <= an_intr_next;
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an_complete_reg <= an_complete_next;
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an_lp_adv_ability_reg <= an_lp_adv_ability_next;
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if (rst) begin
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state_reg <= STATE_START;
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delay_count_reg <= '0;
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delay_run_reg <= 1'b0;
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tx_an_cfg_valid_reg <= 1'b0;
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an_intr_reg <= 1'b0;
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an_complete_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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@@ -20,6 +20,7 @@ module taxi_eth_phy_1g_basex_rx #
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parameter DATA_W = 16,
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parameter CTRL_W = (DATA_W/8),
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parameter logic GBX_IF_EN = 1'b0,
|
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parameter logic AN_EN = 1'b1,
|
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parameter logic BIT_REVERSE = 1'b0,
|
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parameter logic DEC_8B10B_EN = 1'b0,
|
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parameter logic PRBS31_EN = 1'b0,
|
||||
@@ -46,6 +47,15 @@ module taxi_eth_phy_1g_basex_rx #
|
||||
input wire logic serdes_rx_data_valid = 1'b1,
|
||||
output wire logic serdes_rx_reset_req,
|
||||
|
||||
/*
|
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* AN config register
|
||||
*/
|
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output wire logic [15:0] rx_an_cfg,
|
||||
output wire logic rx_an_cfg_valid,
|
||||
output wire logic rx_an_ability_match,
|
||||
output wire logic rx_an_ack_match,
|
||||
output wire logic rx_an_idle_match,
|
||||
|
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/*
|
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* Status
|
||||
*/
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@@ -115,7 +125,7 @@ taxi_gmii_basex_dec #(
|
||||
.DATA_W(DATA_W),
|
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.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.AN_EN(1'b0)
|
||||
.AN_EN(AN_EN)
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||||
)
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dec_inst (
|
||||
.clk(clk),
|
||||
@@ -139,11 +149,11 @@ dec_inst (
|
||||
/*
|
||||
* AN config register
|
||||
*/
|
||||
.rx_an_cfg(),
|
||||
.rx_an_cfg_valid(),
|
||||
.rx_an_ability_match(),
|
||||
.rx_an_ack_match(),
|
||||
.rx_an_idle_match(),
|
||||
.rx_an_cfg(rx_an_cfg),
|
||||
.rx_an_cfg_valid(rx_an_cfg_valid),
|
||||
.rx_an_ability_match(rx_an_ability_match),
|
||||
.rx_an_ack_match(rx_an_ack_match),
|
||||
.rx_an_idle_match(rx_an_idle_match),
|
||||
|
||||
/*
|
||||
* Status
|
||||
|
||||
@@ -20,6 +20,7 @@ module taxi_eth_phy_1g_basex_tx #
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = (DATA_W/8),
|
||||
parameter logic GBX_IF_EN = 1'b0,
|
||||
parameter logic AN_EN = 1'b1,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic ENC_8B10B_EN = 1'b0,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
@@ -52,6 +53,13 @@ module taxi_eth_phy_1g_basex_tx #
|
||||
input wire logic serdes_tx_gbx_req_stall = 1'b0,
|
||||
output wire logic serdes_tx_gbx_sync,
|
||||
|
||||
/*
|
||||
* AN config register
|
||||
*/
|
||||
input wire logic [15:0] tx_an_cfg = '0,
|
||||
input wire logic tx_an_cfg_valid = 1'b0,
|
||||
output wire logic tx_an_cfg_ready,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
@@ -71,7 +79,7 @@ taxi_gmii_basex_enc #(
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.GBX_CNT(1),
|
||||
.AN_EN(1'b0)
|
||||
.AN_EN(AN_EN)
|
||||
)
|
||||
enc_inst (
|
||||
.clk(clk),
|
||||
@@ -99,9 +107,9 @@ enc_inst (
|
||||
/*
|
||||
* AN config register
|
||||
*/
|
||||
.tx_an_cfg('0),
|
||||
.tx_an_cfg_valid(1'b0),
|
||||
.tx_an_cfg_ready()
|
||||
.tx_an_cfg(tx_an_cfg),
|
||||
.tx_an_cfg_valid(tx_an_cfg_valid),
|
||||
.tx_an_cfg_ready(tx_an_cfg_ready)
|
||||
);
|
||||
|
||||
taxi_eth_phy_1g_basex_tx_if #(
|
||||
|
||||
@@ -35,6 +35,7 @@ export PARAM_DATA_W := 16
|
||||
export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_TX_GBX_IF_EN := 0
|
||||
export PARAM_RX_GBX_IF_EN := $(PARAM_TX_GBX_IF_EN)
|
||||
export PARAM_AN_EN := "1'b1"
|
||||
export PARAM_BIT_REVERSE := "1'b0"
|
||||
export PARAM_ENC_8B10B_EN := "1'b0"
|
||||
export PARAM_DEC_8B10B_EN := $(PARAM_ENC_8B10B_EN)
|
||||
|
||||
@@ -75,6 +75,11 @@ class TB:
|
||||
gbx_cfg=gbx_cfg
|
||||
)
|
||||
|
||||
dut.an_en.value = 0
|
||||
dut.an_restart.value = 0
|
||||
dut.an_speedup.value = 1
|
||||
dut.an_adv_ability.value = 0x0020
|
||||
|
||||
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
|
||||
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
|
||||
|
||||
@@ -154,6 +159,73 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_an(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.dut.an_en.value = 1
|
||||
tb.dut.an_restart.value = 0
|
||||
tb.dut.an_speedup.value = 1
|
||||
tb.dut.an_adv_ability.value = 0x0020
|
||||
|
||||
await tb.reset()
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.log.info("AN_RESTART")
|
||||
tb.serdes_source.set_an_cfg(0x0000)
|
||||
|
||||
# link timer
|
||||
for k in range(1250):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.log.info("ABILITY_DETECT")
|
||||
tb.serdes_source.set_an_cfg(0x002A)
|
||||
|
||||
lp_cfg = None
|
||||
while True:
|
||||
await RisingEdge(dut.tx_clk)
|
||||
lp_cfg = tb.serdes_sink.get_an_cfg()
|
||||
if tb.serdes_sink.get_an_ability_match() and lp_cfg is not None and lp_cfg != 0:
|
||||
break
|
||||
|
||||
assert lp_cfg & 0xbfff == int(tb.dut.an_adv_ability.value) & 0xbfff
|
||||
|
||||
tb.log.info("ACKNOWLEDGE_DETECT")
|
||||
tb.serdes_source.set_an_cfg(0x402A)
|
||||
|
||||
while True:
|
||||
await RisingEdge(dut.tx_clk)
|
||||
cfg = tb.serdes_sink.get_an_cfg()
|
||||
if tb.serdes_sink.get_an_ack_match():
|
||||
if lp_cfg | 0x4000 == cfg:
|
||||
break
|
||||
|
||||
tb.log.info("COMPLETE_ACKNOWLEDGE")
|
||||
# link timer
|
||||
for k in range(1250):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
assert lp_cfg & 0xbfff == int(tb.dut.an_adv_ability.value) & 0xbfff
|
||||
assert int(tb.dut.an_lp_adv_ability) & 0xbfff == 0x002A
|
||||
|
||||
tb.log.info("IDLE_DETECT")
|
||||
tb.serdes_source.set_an_cfg(None)
|
||||
|
||||
# link timer
|
||||
for k in range(1250):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
while True:
|
||||
await RisingEdge(dut.tx_clk)
|
||||
if tb.serdes_sink.get_an_idle_match():
|
||||
break
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
@@ -176,6 +248,11 @@ if getattr(cocotb, 'top', None) is not None:
|
||||
factory.add_option("ifg", [12])
|
||||
factory.generate_tests()
|
||||
|
||||
if cocotb.top.AN_EN.value:
|
||||
for test in [run_test_an]:
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
@@ -217,6 +294,7 @@ def test_taxi_eth_phy_1g_basex(request, data_w):
|
||||
parameters['CTRL_W'] = parameters['DATA_W'] // 8
|
||||
parameters['TX_GBX_IF_EN'] = 0
|
||||
parameters['RX_GBX_IF_EN'] = parameters['TX_GBX_IF_EN']
|
||||
parameters['AN_EN'] = "1'b1"
|
||||
parameters['BIT_REVERSE'] = "1'b0"
|
||||
parameters['ENC_8B10B_EN'] = "1'b0"
|
||||
parameters['DEC_8B10B_EN'] = parameters['ENC_8B10B_EN']
|
||||
|
||||
Reference in New Issue
Block a user