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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-08-04 17:40:45 -07:00
parent 927d259b57
commit e7fd1b6c22
29 changed files with 63 additions and 36 deletions
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2
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
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@@ -172,7 +172,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_qsfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv
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@@ -173,7 +173,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
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@@ -343,7 +343,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(eth_gty_axis_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/HTG9200/fpga/rtl/fpga_core.sv
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@@ -424,7 +424,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(eth_gty_axis_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv
View File

@@ -368,7 +368,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(eth_gty_axis_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv
View File

@@ -516,7 +516,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

5
src/eth/example/KCU105/fpga/fpga_10g/config.tcl
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@@ -12,6 +12,11 @@ set params [dict create]
# 0 for 1G, 1 for 10G
dict set params SFP_RATE "1"
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "32"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {

5
src/eth/example/KCU105/fpga/fpga_1g/config.tcl
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@@ -12,6 +12,11 @@ set params [dict create]
# 0 for 1G, 1 for 10G
dict set params SFP_RATE "0"
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "1"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "16"
# apply parameters to top-level
set param_list {}
dict for {name value} $params {

11
src/eth/example/KCU105/fpga/rtl/fpga.sv
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@@ -24,7 +24,11 @@ module fpga #
// device family
parameter string FAMILY = "kintexu",
// SFP rate selection (0 for 1G, 1 for 10G)
parameter logic SFP_RATE = 1'b1
parameter logic SFP_RATE = 1'b1,
// 10G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = SFP_RATE ? 32 : 16
)
(
/*
@@ -379,7 +383,10 @@ fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
.SFP_RATE(SFP_RATE)
.SFP_RATE(SFP_RATE),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.MAC_DATA_W(MAC_DATA_W)
)
core_inst (
/*

18
src/eth/example/KCU105/fpga/rtl/fpga_core.sv
View File

@@ -24,7 +24,11 @@ module fpga_core #
// device family
parameter string FAMILY = "kintexu",
// SFP rate selection (0 for 1G, 1 for 10G)
parameter logic SFP_RATE = 1'b1
parameter logic SFP_RATE = 1'b1,
// 10G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = SFP_RATE ? 32 : 16
)
(
/*
@@ -328,11 +332,9 @@ wire sfp_mgt_refclk_0_bufg;
wire sfp_rst;
localparam SFP_DATA_W = SFP_RATE ? 32 : 16;
taxi_axis_if #(.DATA_W(SFP_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
taxi_axis_if #(.DATA_W(SFP_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2]();
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2]();
if (SIM) begin
@@ -406,12 +408,13 @@ if (SFP_RATE == 0) begin : sfp_mac
.CNT(2),
// GT config
.CFG_LOW_LATENCY(1),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
// GT type
.GT_TYPE("GTH"),
// PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.SGMII_EN(1'b1),
.AN_EN(1'b1),
.DIC_EN(1'b1),
@@ -673,12 +676,13 @@ end else begin : sfp_mac
.CNT(2),
// GT config
.CFG_LOW_LATENCY(1),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
// GT type
.GT_TYPE("GTH"),
// PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(1'b1),
.DIC_EN(1'b1),

3
src/eth/example/KCU105/fpga/tb/fpga_core/Makefile
View File

@@ -46,6 +46,9 @@ export PARAM_SIM := "1'b1"
export PARAM_VENDOR := "\"XILINX\""
export PARAM_FAMILY := "\"kintexu\""
export PARAM_SFP_RATE := "1'b1"
export PARAM_CFG_LOW_LATENCY := "1'b1"
export PARAM_COMBINED_MAC_PCS := "1'b1"
export PARAM_MAC_DATA_W := "32"
ifeq ($(SIM), icarus)
PLUSARGS += -fst

7
src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
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@@ -245,8 +245,8 @@ def process_f_files(files):
return list(lst.values())
@pytest.mark.parametrize("sfp_rate", [0, 1])
def test_fpga_core(request, sfp_rate):
@pytest.mark.parametrize(("sfp_rate", "mac_data_w"), [(0, 16), (1, 32), (1, 64)])
def test_fpga_core(request, sfp_rate, mac_data_w):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
@@ -274,6 +274,9 @@ def test_fpga_core(request, sfp_rate):
parameters['VENDOR'] = "\"XILINX\""
parameters['FAMILY'] = "\"kintexu\""
parameters['SFP_RATE'] = f"1'b{sfp_rate}"
parameters['CFG_LOW_LATENCY'] = "1'b1"
parameters['COMBINED_MAC_PCS'] = "1'b1"
parameters['MAC_DATA_W'] = mac_data_w
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

2
src/eth/example/KR260/fpga/rtl/fpga_core.sv
View File

@@ -416,7 +416,7 @@ end else begin : sfp_mac
// PHY parameters
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(1'b1),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/NT200A02/fpga/rtl/fpga_core.sv
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@@ -201,7 +201,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(eth_gty_axis_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/NT40E3/fpga/rtl/fpga_core.sv
View File

@@ -158,7 +158,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(1'b1),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv
View File

@@ -305,7 +305,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(1'b1),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv
View File

@@ -191,7 +191,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_qsfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv
View File

@@ -167,7 +167,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
View File

@@ -371,7 +371,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_qsfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/VC709/fpga/rtl/fpga_core.sv
View File

@@ -310,7 +310,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(MAC_DATA_W),
.USXGMII_EN(1'b1),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/VCU108/fpga/rtl/fpga_core.sv
View File

@@ -398,7 +398,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_qsfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/VCU118/fpga/rtl/fpga_core.sv
View File

@@ -595,7 +595,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_qsfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv
View File

@@ -322,7 +322,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(eth_gty_axis_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/ZCU102/fpga/rtl/fpga.sv
View File

@@ -28,7 +28,7 @@ module fpga #
// 10G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 32
parameter MAC_DATA_W = SFP_RATE ? 32 : 16
)
(
/*

4
src/eth/example/ZCU102/fpga/rtl/fpga_core.sv
View File

@@ -28,7 +28,7 @@ module fpga_core #
// 10G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 32
parameter MAC_DATA_W = SFP_RATE ? 32 : 16
)
(
/*
@@ -547,7 +547,7 @@ end else begin : sfp_mac
// PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/ZCU106/fpga/rtl/fpga.sv
View File

@@ -28,7 +28,7 @@ module fpga #
// 10G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 32
parameter MAC_DATA_W = SFP_RATE ? 32 : 16
)
(
/*

4
src/eth/example/ZCU106/fpga/rtl/fpga_core.sv
View File

@@ -28,7 +28,7 @@ module fpga_core #
// 10G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 32
parameter MAC_DATA_W = SFP_RATE ? 32 : 16
)
(
/*
@@ -548,7 +548,7 @@ end else begin : sfp_mac
// PHY parameters
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/ZCU111/fpga/rtl/fpga_core.sv
View File

@@ -379,7 +379,7 @@ taxi_eth_mac_25g_us #(
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_sfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),

2
src/eth/example/fb2CG/fpga/rtl/fpga_core.sv
View File

@@ -219,7 +219,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
// MAC/PHY config
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.DATA_W(axis_qsfp_tx[0].DATA_W),
.USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32),
.USXGMII_EN(COMBINED_MAC_PCS),
.DIC_EN(1'b1),
.PTP_TS_EN(1'b0),
.PTP_TD_EN(1'b0),