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5b14329483af189730841ccde443da7a9b4c2da4
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2 Commits

Author SHA1 Message Date
Alex Forencich
5b14329483 axi: Clean up user signal width handling in AXI RAM IF modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2026-03-20 00:06:23 -07:00
Alex Forencich
5652bb0016 axi: Add AXI RAM interface and AXI dual port RAM 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2026-03-19 18:12:37 -07:00