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94dba885606414b3fe59b63c146f54c9b0488236
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2 Commits

Author SHA1 Message Date
Alex Forencich
d01a90298c eth: Use correct clock for TX completions in MAC + FIFO testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-16 18:59:18 -08:00
Alex Forencich
2abe774f8a eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-13 13:48:54 -08:00