Alex Forencich
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c0a164a1d2
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axis: Add AXI stream adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:33:29 -08:00 |
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Alex Forencich
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03c0883356
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axis: Add AXI stream FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 22:43:17 -08:00 |
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Alex Forencich
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9590811570
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axis: Add AXI stream pipeline FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:35:52 -08:00 |
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Alex Forencich
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47e4658b55
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axis: Add AXI stream pipeline register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:35:25 -08:00 |
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Alex Forencich
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c4558a02f0
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lss: Add UART module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 15:02:48 -08:00 |
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Alex Forencich
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c7f719b435
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axis: Add AXI stream register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 12:49:08 -08:00 |
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Alex Forencich
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e1233eaffe
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axis: Add SV interface for AXI stream
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-02 22:45:12 -08:00 |
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