Alex Forencich 0080125120 axi: Add AXI to AXI lite adapter module and testbench ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-08-30 21:11:20 -07:00

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axi

axi: Add AXI to AXI lite adapter module and testbench

2025-08-30 21:11:20 -07:00

axis

axis: Add AXI stream tie and null source/sink modules

2025-08-20 06:33:21 -07:00

eth

eth: Add RFDC to ZCU111 example design

2025-08-24 11:26:14 -07:00

hip/rtl/us

eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers

2025-05-21 21:06:45 -07:00

io/rtl

Reorganize repository

2025-05-18 12:25:59 -07:00

lfsr

lfsr: Merge output state with data when possible

2025-06-11 18:48:07 -07:00

lss

lss: Optimize delay implementation in I2C master module

2025-08-24 11:30:03 -07:00

pcie

pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master

2025-08-29 17:59:56 -07:00

prim

Reorganize repository

2025-05-18 12:25:59 -07:00

ptp

ptp: Adjust testbench thresholds

2025-05-30 22:11:36 -07:00

stats

Reorganize repository

2025-05-18 12:25:59 -07:00

sync

Reorganize repository

2025-05-18 12:25:59 -07:00

xfcp

xfcp: Fix width

2025-08-24 11:26:25 -07:00

zircon

zircon: tdest not used on TX path after length/checksum computation, which also extracts the tdest value

2025-08-15 13:36:14 -07:00