Reorganize repository

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/ADM_PCIE_9V3/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/Alveo/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/Alveo/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/Arty/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/HTG940/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/KC705/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/KCU105/fpga/fpga_10g/Makefile

@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xcku040-ffva1156-2-e
-FPGA_TOP = fpga
-FPGA_ARCH = kintexu
-
-# Files for synthesis
-SYN_FILES = ../rtl/fpga.sv
-SYN_FILES += ../rtl/fpga_core.sv
-SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
-SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
-SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
-
-# XDC files
-XDC_FILES = ../fpga.xdc
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
-
-# IP
-IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
-
-# Configuration
-CONFIG_TCL_FILES = ./config.tcl
-
-include ../common/vivado.mk
-
-program: $(PROJECT).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl

example/KCU105/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/KCU105/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/KR260/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/KR260/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/Nexus_K3P_Q/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/Nexus_K3P_S/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/VCU108/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/VCU108/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/VCU118/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/VCU118/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/XUPP3R/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/XUPP3R/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/ZCU102/fpga/fpga_10g/Makefile

@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xczu9eg-ffvb1156-2-e
-FPGA_TOP = fpga
-FPGA_ARCH = zynquplus
-
-# Files for synthesis
-SYN_FILES = ../rtl/fpga.sv
-SYN_FILES += ../rtl/fpga_core.sv
-SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
-SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
-SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
-
-# XDC files
-XDC_FILES = ../fpga.xdc
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
-
-# IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
-
-# Configuration
-CONFIG_TCL_FILES = ./config.tcl
-
-include ../common/vivado.mk
-
-program: $(FPGA_TOP).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl
-

example/ZCU102/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/ZCU102/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/ZCU106/fpga/fpga_10g/Makefile

@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xczu7ev-ffvc1156-2-e
-FPGA_TOP = fpga
-FPGA_ARCH = zynquplus
-
-# Files for synthesis
-SYN_FILES = ../rtl/fpga.sv
-SYN_FILES += ../rtl/fpga_core.sv
-SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
-SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
-SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
-
-# XDC files
-XDC_FILES = ../fpga.xdc
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
-
-# IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
-
-# Configuration
-CONFIG_TCL_FILES = ./config.tcl
-
-include ../common/vivado.mk
-
-program: $(FPGA_TOP).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl
-

example/ZCU106/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/ZCU106/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/ZCU111/fpga/fpga/Makefile

@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xczu28dr-ffvg1517-2-e
-FPGA_TOP = fpga
-FPGA_ARCH = zynquplus
-
-# Files for synthesis
-SYN_FILES = ../rtl/fpga.sv
-SYN_FILES += ../rtl/fpga_core.sv
-SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
-SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
-SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
-
-# XDC files
-XDC_FILES = ../fpga.xdc
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
-
-# IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
-
-# Configuration
-#CONFIG_TCL_FILES = ./config.tcl
-
-include ../common/vivado.mk
-
-program: $(FPGA_TOP).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl
-

example/ZCU111/fpga/fpga_10g/Makefile

@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2025 FPGA Ninja, LLC
-#
-# Authors:
-# - Alex Forencich
-#
-
-# FPGA settings
-FPGA_PART = xczu28dr-ffvg1517-2-e
-FPGA_TOP = fpga
-FPGA_ARCH = zynquplus
-
-# Files for synthesis
-SYN_FILES = ../rtl/fpga.sv
-SYN_FILES += ../rtl/fpga_core.sv
-SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
-SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
-SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
-SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
-SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
-
-# XDC files
-XDC_FILES = ../fpga.xdc
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
-XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
-
-# IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
-
-# Configuration
-#CONFIG_TCL_FILES = ./config.tcl
-
-include ../common/vivado.mk
-
-program: $(FPGA_TOP).bit
-	echo "open_hw_manager" > program.tcl
-	echo "connect_hw_server" >> program.tcl
-	echo "open_hw_target" >> program.tcl
-	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
-	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
-	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
-	echo "program_hw_devices [current_hw_device]" >> program.tcl
-	echo "exit" >> program.tcl
-	vivado -nojournal -nolog -mode batch -source program.tcl
-

example/ZCU111/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/ZCU111/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

example/fb2CG/fpga/lib/taxi

@@ -1 +0,0 @@
-../../../../

example/fb2CG/fpga/tb/fpga_core/baser.py

@@ -1 +0,0 @@
-../../lib/taxi/tb/eth/baser.py

rtl/axis/taxi_axis_arb_mux.f

@@ -1,4 +0,0 @@
-taxi_axis_arb_mux.sv
-taxi_axis_if.sv
-../prim/taxi_arbiter.sv
-../prim/taxi_penc.sv

rtl/axis/taxi_axis_async_fifo.f

@@ -1,4 +0,0 @@
-taxi_axis_async_fifo.sv
-../sync/taxi_sync_reset.sv
-../sync/taxi_sync_signal.sv
-taxi_axis_if.sv

rtl/eth/taxi_eth_mac_10g_fifo.f

@@ -1,4 +0,0 @@
-taxi_eth_mac_10g_fifo.sv
-taxi_eth_mac_10g.f
-../ptp/taxi_ptp_clock_cdc.sv
-../axis/taxi_axis_async_fifo_adapter.f

rtl/eth/taxi_eth_mac_1g_fifo.f

@@ -1,3 +0,0 @@
-taxi_eth_mac_1g_fifo.sv
-taxi_eth_mac_1g.f
-../axis/taxi_axis_async_fifo_adapter.f

rtl/eth/taxi_eth_mac_1g_gmii_fifo.f

@@ -1,3 +0,0 @@
-taxi_eth_mac_1g_gmii_fifo.sv
-taxi_eth_mac_1g_gmii.f
-../axis/taxi_axis_async_fifo_adapter.f

rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f

@@ -1,3 +0,0 @@
-taxi_eth_mac_1g_rgmii_fifo.sv
-taxi_eth_mac_1g_rgmii.f
-../axis/taxi_axis_async_fifo_adapter.f

rtl/eth/taxi_eth_mac_mii_fifo.f

@@ -1,3 +0,0 @@
-taxi_eth_mac_mii_fifo.sv
-taxi_eth_mac_mii.f
-../axis/taxi_axis_async_fifo_adapter.f

rtl/eth/taxi_eth_mac_phy_10g_fifo.f

@@ -1,4 +0,0 @@
-taxi_eth_mac_phy_10g_fifo.sv
-taxi_eth_mac_phy_10g.f
-../ptp/taxi_ptp_clock_cdc.sv
-../axis/taxi_axis_async_fifo_adapter.f

rtl/eth/taxi_eth_mac_phy_10g_rx.f

@@ -1,5 +0,0 @@
-taxi_eth_mac_phy_10g_rx.sv
-taxi_eth_phy_10g_rx_if.f
-taxi_axis_baser_rx_64.sv
-../lfsr/taxi_lfsr.sv
-../axis/taxi_axis_if.sv

rtl/eth/taxi_eth_mac_phy_10g_tx.f

@@ -1,5 +0,0 @@
-taxi_eth_mac_phy_10g_tx.sv
-taxi_eth_phy_10g_tx_if.f
-taxi_axis_baser_tx_64.sv
-../lfsr/taxi_lfsr.sv
-../axis/taxi_axis_if.sv

rtl/eth/taxi_eth_mac_stats.f

@@ -1,4 +0,0 @@
-taxi_eth_mac_stats.sv
-../axis/taxi_axis_async_fifo.f
-../axis/taxi_axis_arb_mux.f
-../stats/taxi_stats_collect.sv

rtl/eth/taxi_eth_phy_10g_tx_if.f

@@ -1,2 +0,0 @@
-taxi_eth_phy_10g_tx_if.sv
-../lfsr/taxi_lfsr.sv

rtl/eth/taxi_gmii_phy_if.f

@@ -1,5 +0,0 @@
-taxi_gmii_phy_if.sv
-../io/taxi_ssio_sdr_in.sv
-../io/taxi_ssio_sdr_out.sv
-../io/taxi_oddr.sv
-../sync/taxi_sync_reset.sv

rtl/eth/taxi_mii_phy_if.f

@@ -1,3 +0,0 @@
-taxi_mii_phy_if.sv
-../io/taxi_ssio_sdr_in.sv
-../sync/taxi_sync_reset.sv

rtl/eth/taxi_rgmii_phy_if.f

@@ -1,5 +0,0 @@
-taxi_rgmii_phy_if.sv
-../io/taxi_ssio_ddr_in.sv
-../io/taxi_iddr.sv
-../io/taxi_oddr.sv
-../sync/taxi_sync_reset.sv

rtl/eth/us/taxi_eth_phy_25g_us_gt.f

@@ -1,2 +0,0 @@
-taxi_eth_phy_25g_us_gt.sv
-../../sync/taxi_sync_reset.sv

rtl/xfcp/taxi_xfcp_if_uart.f

@@ -1,5 +0,0 @@
-taxi_xfcp_if_uart.sv
-../lss/taxi_uart.f
-../axis/taxi_axis_fifo.sv
-../axis/taxi_axis_cobs_encode.f
-../axis/taxi_axis_cobs_decode.sv

rtl/xfcp/taxi_xfcp_mod_axi.f

@@ -1,5 +0,0 @@
-taxi_xfcp_mod_axi.sv
-taxi_xfcp_mod_axil.sv
-../axi/taxi_axi_if.sv
-../axi/taxi_axil_if.sv
-../axis/taxi_axis_if.sv

rtl/xfcp/taxi_xfcp_mod_i2c_master.f

@@ -1,3 +0,0 @@
-taxi_xfcp_mod_i2c_master.sv
-../lss/taxi_i2c_master.sv
-../axis/taxi_axis_if.sv

rtl/xfcp/taxi_xfcp_mod_stats.f

@@ -1,7 +0,0 @@
-taxi_xfcp_mod_stats.sv
-taxi_xfcp_mod_axil.sv
-taxi_xfcp_switch.f
-../stats/taxi_stats_counter.sv
-../stats/taxi_stats_strings_full.sv
-../axi/taxi_axil_if.sv
-../axis/taxi_axis_if.sv

rtl/xfcp/taxi_xfcp_switch.f

@@ -1,4 +0,0 @@
-taxi_xfcp_switch.sv
-../prim/taxi_arbiter.sv
-../prim/taxi_penc.sv
-../axis/taxi_axis_if.sv

src/axi/lib/taxi

@@ -0,0 +1 @@
+../../../

src/axi/tb/taxi_axi_ram/Makefile

@@ -13,14 +13,18 @@ WAVES ?= 0
 COCOTB_HDL_TIMEUNIT = 1ns
 COCOTB_HDL_TIMEPRECISION = 1ps
 
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
 DUT      = taxi_axi_ram
 COCOTB_TEST_MODULES = test_$(DUT)
 COCOTB_TOPLEVEL     = test_$(DUT)
 MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
-VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv
-VERILOG_SOURCES += ../../../rtl/axi/taxi_axi_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_axi_if.sv
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py

@@ -186,7 +186,9 @@ if cocotb.SIM_NAME:
 # cocotb-test
 
 tests_dir = os.path.abspath(os.path.dirname(__file__))
-rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
 
 
 def process_f_files(files):
@@ -210,8 +212,8 @@ def test_taxi_axi_ram(request, data_w):
 
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
-        os.path.join(rtl_dir, "axi", f"{dut}.sv"),
-        os.path.join(rtl_dir, "axi", "taxi_axi_if.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_axi_if.sv"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)

src/axi/tb/taxi_axi_register/Makefile

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: CERN-OHL-S-2.0
 #
 # Copyright (c) 2020-2025
+#
 # Authors:
 # - Alex Forencich
 
@@ -12,13 +13,17 @@ WAVES ?= 0
 COCOTB_HDL_TIMEUNIT = 1ns
 COCOTB_HDL_TIMEPRECISION = 1ps
 
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
 DUT      = taxi_axi_register
 COCOTB_TEST_MODULES = test_$(DUT)
 COCOTB_TOPLEVEL     = test_$(DUT)
 MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
-VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

src/axi/tb/taxi_axi_register/test_taxi_axi_register.py

@@ -194,7 +194,9 @@ if cocotb.SIM_NAME:
 # cocotb-test
 
 tests_dir = os.path.abspath(os.path.dirname(__file__))
-rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
 
 
 def process_f_files(files):
@@ -219,7 +221,7 @@ def test_taxi_axi_register(request, data_w, reg_type):
 
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
-        os.path.join(rtl_dir, "axi", f"{dut}.f"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)

src/axi/tb/taxi_axil_dp_ram/Makefile

@@ -13,14 +13,18 @@ WAVES ?= 0
 COCOTB_HDL_TIMEUNIT = 1ns
 COCOTB_HDL_TIMEPRECISION = 1ps
 
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
 DUT      = taxi_axil_dp_ram
 COCOTB_TEST_MODULES = test_$(DUT)
 COCOTB_TOPLEVEL     = test_$(DUT)
 MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
-VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv
-VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py

@@ -220,7 +220,9 @@ if cocotb.SIM_NAME:
 # cocotb-test
 
 tests_dir = os.path.abspath(os.path.dirname(__file__))
-rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
 
 
 def process_f_files(files):
@@ -244,8 +246,8 @@ def test_taxi_axil_dp_ram(request, data_w):
 
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
-        os.path.join(rtl_dir, "axi", f"{dut}.sv"),
-        os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_axil_if.sv"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)

src/axi/tb/taxi_axil_ram/Makefile

@@ -13,14 +13,18 @@ WAVES ?= 0
 COCOTB_HDL_TIMEUNIT = 1ns
 COCOTB_HDL_TIMEPRECISION = 1ps
 
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
 DUT      = taxi_axil_ram
 COCOTB_TEST_MODULES = test_$(DUT)
 COCOTB_TOPLEVEL     = test_$(DUT)
 MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
-VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv
-VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py

@@ -168,7 +168,9 @@ if cocotb.SIM_NAME:
 # cocotb-test
 
 tests_dir = os.path.abspath(os.path.dirname(__file__))
-rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
 
 
 def process_f_files(files):
@@ -192,8 +194,8 @@ def test_taxi_axil_ram(request, data_w):
 
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
-        os.path.join(rtl_dir, "axi", f"{dut}.sv"),
-        os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_axil_if.sv"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)

src/axi/tb/taxi_axil_register/Makefile

@@ -13,13 +13,17 @@ WAVES ?= 0
 COCOTB_HDL_TIMEUNIT = 1ns
 COCOTB_HDL_TIMEPRECISION = 1ps
 
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
 DUT      = taxi_axil_register
 COCOTB_TEST_MODULES = test_$(DUT)
 COCOTB_TOPLEVEL     = test_$(DUT)
 MODULE   = $(COCOTB_TEST_MODULES)
 TOPLEVEL = $(COCOTB_TOPLEVEL)
 VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
-VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
 
 # handle file list files
 process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))

src/axi/tb/taxi_axil_register/test_taxi_axil_register.py

@@ -176,7 +176,9 @@ if cocotb.SIM_NAME:
 # cocotb-test
 
 tests_dir = os.path.abspath(os.path.dirname(__file__))
-rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
 
 
 def process_f_files(files):
@@ -201,7 +203,7 @@ def test_taxi_axil_register(request, data_w, reg_type):
 
     verilog_sources = [
         os.path.join(tests_dir, f"{toplevel}.sv"),
-        os.path.join(rtl_dir, "axi", f"{dut}.f"),
+        os.path.join(rtl_dir, f"{dut}.f"),
     ]
 
     verilog_sources = process_f_files(verilog_sources)

src/axis/lib/taxi

@@ -0,0 +1 @@
+../../../

src/axis/rtl/taxi_axis_arb_mux.f

@@ -0,0 +1,4 @@
+taxi_axis_arb_mux.sv
+taxi_axis_if.sv
+../lib/taxi/src/prim/rtl/taxi_arbiter.sv
+../lib/taxi/src/prim/rtl/taxi_penc.sv

src/axis/rtl/taxi_axis_async_fifo.f

@@ -0,0 +1,4 @@
+taxi_axis_async_fifo.sv
+../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
+../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
+taxi_axis_if.sv