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04b73e7ddfac28b9b018aab76fa7803c27525ea5
taxi/rtl/eth
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Alex Forencich 04b73e7ddf eth: Add 1G Ethernet MAC module with FIFOs and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-11 22:12:57 -08:00
..
taxi_axis_baser_rx_64.sv
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
2025-02-07 16:27:27 -08:00
taxi_axis_baser_tx_64.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_axis_gmii_rx.sv
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
2025-02-07 16:12:58 -08:00
taxi_axis_gmii_tx.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_axis_xgmii_rx_32.sv
eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
2025-02-07 16:25:06 -08:00
taxi_axis_xgmii_rx_64.sv
eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
2025-02-07 16:25:54 -08:00
taxi_axis_xgmii_tx_32.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_axis_xgmii_tx_64.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_eth_mac_1g_fifo.f
eth: Add 1G Ethernet MAC module with FIFOs and testbench
2025-02-11 22:12:57 -08:00
taxi_eth_mac_1g_fifo.sv
eth: Add 1G Ethernet MAC module with FIFOs and testbench
2025-02-11 22:12:57 -08:00
taxi_eth_mac_1g.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_1g.sv
eth: Add 1G Ethernet MAC module and testbench
2025-02-08 21:25:48 -08:00
taxi_eth_mac_10g.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_10g.sv
eth: Add 10G Ethernet MAC module and testbench
2025-02-08 21:26:03 -08:00
taxi_eth_mac_phy_10g_rx.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_phy_10g_rx.sv
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_mac_phy_10g_tx.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_phy_10g_tx.sv
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_mac_phy_10g.f
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_mac_phy_10g.sv
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_phy_10g_rx_ber_mon.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_frame_sync.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_if.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_if.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_watchdog.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx_if.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx_if.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_mac_ctrl_rx.sv
eth: Add MAC control modules
2025-02-08 19:59:11 -08:00
taxi_mac_ctrl_tx.sv
eth: Add MAC control modules
2025-02-08 19:59:11 -08:00
taxi_mac_pause_ctrl_rx.sv
eth: Add MAC pause control modules
2025-02-05 21:11:14 -08:00
taxi_mac_pause_ctrl_tx.sv
eth: Add MAC pause control modules
2025-02-05 21:11:14 -08:00
taxi_xgmii_baser_dec_64.sv
eth: Add XGMII/BASE-R encode/decode modules and testbenches
2025-02-04 16:14:32 -08:00
taxi_xgmii_baser_enc_64.sv
eth: Add XGMII/BASE-R encode/decode modules and testbenches
2025-02-04 16:14:32 -08:00