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mirror of https://github.com/fpganinja/taxi.git synced 2026-01-19 01:40:19 -08:00
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0ee729b7440a75b3bf225c15861ec3c53df22faf
taxi/example/Alveo/fpga/rtl
History
Alex Forencich ed9e8ffab3 eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-03-07 11:05:58 -08:00
..
fpga_au45n.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au50.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au55.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au200.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au280.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_core.sv
eth: Use unpacked arrays for multidimensional ports
2025-03-07 11:05:58 -08:00
fpga_x3522.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
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